From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs Date: Thu, 21 Apr 2016 22:12:28 +0100 Message-ID: <20160421221228.359fab3c@arm.com> References: <1461122150-9042-1-git-send-email-jay.xu@rock-chips.com> <5718AFB8.5070004@rock-chips.com> <20160421123018.096d4a75@arm.com> <2131452.5tyGOfVRfi@diego> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <2131452.5tyGOfVRfi@diego> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Heiko =?ISO-8859-1?Q?St=FCbner?= Cc: "Huang, Tao" , Mark Rutland , Jianqun Xu , will.deacon-5wv7dgnIgG8@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, catalin.marinas-5wv7dgnIgG8@public.gmane.org, davidriley-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, jwerner-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, smbarber-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-rockchip.vger.kernel.org On Thu, 21 Apr 2016 22:24:09 +0200 Heiko St=C3=BCbner wrote: > Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier: > > On Thu, 21 Apr 2016 18:47:20 +0800 > >=20 > > "Huang, Tao" wrote: > > > Hi, Mark: > > >=20 > > > On 2016=E5=B9=B404=E6=9C=8821=E6=97=A5 18:19, Mark Rutland wrote: > > > > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote: > > > >> + cpu_l0: cpu@0 { > > > >> + device_type =3D "cpu"; > > > >> + compatible =3D "arm,cortex-a53", "arm,armv8"; > > > >> + reg =3D <0x0 0x0>; > > > >> + enable-method =3D "psci"; > > > >> + #cooling-cells =3D <2>; /* min followed by max */ > > > >> + clocks =3D <&cru ARMCLKL>; > > > >> + }; > > > >> + cpu_b0: cpu@100 { > > > >> + device_type =3D "cpu"; > > > >> + compatible =3D "arm,cortex-a72", "arm,armv8"; > > > >> + reg =3D <0x0 0x100>; > > > >> + enable-method =3D "psci"; > > > >> + #cooling-cells =3D <2>; /* min followed by max */ > > > >> + clocks =3D <&cru ARMCLKB>; > > > >> + }; > > > >> + > > > >> + arm-pmu { > > > >> + compatible =3D "arm,armv8-pmuv3"; > > > >> + interrupts =3D ; > > > >> + }; > > > >=20 > > > > This is wrong, and must go. There should be a separate node for= the PMU > > > > of each microarchitecture, with the appropriate compatible stri= ng to > > > > represent that (see the juno dts). > > >=20 > > > You are right. The first version we wrote is: > > > pmu_a53 { > > > =20 > > > compatible =3D "arm,cortex-a53-pmu"; > > > interrupts =3D ; > > > interrupt-affinity =3D <&cpu_l0>, > > > =20 > > > <&cpu_l1>, > > > <&cpu_l2>, > > > <&cpu_l3>; > > > =20 > > > }; > > > =20 > > > pmu_a72 { > > > =20 > > > compatible =3D "arm,cortex-a72-pmu"; > > > interrupts =3D ; > > > interrupt-affinity =3D <&cpu_b0>, > > > =20 > > > <&cpu_b1>; > > > =20 > > > }; > > >=20 > > > but unfortunately, the arm pmu driver do not support PPI in two c= luster > > > well, > > > so we have to replace with this implementation. > > >=20 > > > > In this case things are messier as the same PPI number is being= used > > > > across clusters. Marc (Cc'd) has been working on PPI partitions= , which > > > > should allow us to support that. > > >=20 > > > Great! So what we can do right now? Wait this feature, and delete > > > arm-pmu node? > >=20 > > I'd rather you have a look at the patches, test them with your HW, > > and comment on what doesn't work! >=20 > I would think we could do it in two tracks, testing and fixing but al= so letting=20 > the rk3399 devicetrees move forward without the pmu at first :-) . Where would the fun be then? ;-) M. --=20 Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe devicetree" i= n the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Thu, 21 Apr 2016 22:12:28 +0100 Subject: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs In-Reply-To: <2131452.5tyGOfVRfi@diego> References: <1461122150-9042-1-git-send-email-jay.xu@rock-chips.com> <5718AFB8.5070004@rock-chips.com> <20160421123018.096d4a75@arm.com> <2131452.5tyGOfVRfi@diego> Message-ID: <20160421221228.359fab3c@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, 21 Apr 2016 22:24:09 +0200 Heiko St?bner wrote: > Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier: > > On Thu, 21 Apr 2016 18:47:20 +0800 > > > > "Huang, Tao" wrote: > > > Hi, Mark: > > > > > > On 2016?04?21? 18:19, Mark Rutland wrote: > > > > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote: > > > >> + cpu_l0: cpu at 0 { > > > >> + device_type = "cpu"; > > > >> + compatible = "arm,cortex-a53", "arm,armv8"; > > > >> + reg = <0x0 0x0>; > > > >> + enable-method = "psci"; > > > >> + #cooling-cells = <2>; /* min followed by max */ > > > >> + clocks = <&cru ARMCLKL>; > > > >> + }; > > > >> + cpu_b0: cpu at 100 { > > > >> + device_type = "cpu"; > > > >> + compatible = "arm,cortex-a72", "arm,armv8"; > > > >> + reg = <0x0 0x100>; > > > >> + enable-method = "psci"; > > > >> + #cooling-cells = <2>; /* min followed by max */ > > > >> + clocks = <&cru ARMCLKB>; > > > >> + }; > > > >> + > > > >> + arm-pmu { > > > >> + compatible = "arm,armv8-pmuv3"; > > > >> + interrupts = ; > > > >> + }; > > > > > > > > This is wrong, and must go. There should be a separate node for the PMU > > > > of each microarchitecture, with the appropriate compatible string to > > > > represent that (see the juno dts). > > > > > > You are right. The first version we wrote is: > > > pmu_a53 { > > > > > > compatible = "arm,cortex-a53-pmu"; > > > interrupts = ; > > > interrupt-affinity = <&cpu_l0>, > > > > > > <&cpu_l1>, > > > <&cpu_l2>, > > > <&cpu_l3>; > > > > > > }; > > > > > > pmu_a72 { > > > > > > compatible = "arm,cortex-a72-pmu"; > > > interrupts = ; > > > interrupt-affinity = <&cpu_b0>, > > > > > > <&cpu_b1>; > > > > > > }; > > > > > > but unfortunately, the arm pmu driver do not support PPI in two cluster > > > well, > > > so we have to replace with this implementation. > > > > > > > In this case things are messier as the same PPI number is being used > > > > across clusters. Marc (Cc'd) has been working on PPI partitions, which > > > > should allow us to support that. > > > > > > Great! So what we can do right now? Wait this feature, and delete > > > arm-pmu node? > > > > I'd rather you have a look at the patches, test them with your HW, > > and comment on what doesn't work! > > I would think we could do it in two tracks, testing and fixing but also letting > the rk3399 devicetrees move forward without the pmu at first :-) . Where would the fun be then? ;-) M. -- Jazz is not dead. It just smells funny. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753346AbcDUVMl (ORCPT ); Thu, 21 Apr 2016 17:12:41 -0400 Received: from foss.arm.com ([217.140.101.70]:57654 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751957AbcDUVMj convert rfc822-to-8bit (ORCPT ); Thu, 21 Apr 2016 17:12:39 -0400 Date: Thu, 21 Apr 2016 22:12:28 +0100 From: Marc Zyngier To: Heiko =?ISO-8859-1?Q?St=FCbner?= Cc: "Huang, Tao" , Mark Rutland , Jianqun Xu , , , , , , , , , , , , , , Subject: Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs Message-ID: <20160421221228.359fab3c@arm.com> In-Reply-To: <2131452.5tyGOfVRfi@diego> References: <1461122150-9042-1-git-send-email-jay.xu@rock-chips.com> <5718AFB8.5070004@rock-chips.com> <20160421123018.096d4a75@arm.com> <2131452.5tyGOfVRfi@diego> Organization: ARM Ltd X-Mailer: Claws Mail 3.11.1 (GTK+ 2.24.25; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 21 Apr 2016 22:24:09 +0200 Heiko Stübner wrote: > Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier: > > On Thu, 21 Apr 2016 18:47:20 +0800 > > > > "Huang, Tao" wrote: > > > Hi, Mark: > > > > > > On 2016年04月21日 18:19, Mark Rutland wrote: > > > > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote: > > > >> + cpu_l0: cpu@0 { > > > >> + device_type = "cpu"; > > > >> + compatible = "arm,cortex-a53", "arm,armv8"; > > > >> + reg = <0x0 0x0>; > > > >> + enable-method = "psci"; > > > >> + #cooling-cells = <2>; /* min followed by max */ > > > >> + clocks = <&cru ARMCLKL>; > > > >> + }; > > > >> + cpu_b0: cpu@100 { > > > >> + device_type = "cpu"; > > > >> + compatible = "arm,cortex-a72", "arm,armv8"; > > > >> + reg = <0x0 0x100>; > > > >> + enable-method = "psci"; > > > >> + #cooling-cells = <2>; /* min followed by max */ > > > >> + clocks = <&cru ARMCLKB>; > > > >> + }; > > > >> + > > > >> + arm-pmu { > > > >> + compatible = "arm,armv8-pmuv3"; > > > >> + interrupts = ; > > > >> + }; > > > > > > > > This is wrong, and must go. There should be a separate node for the PMU > > > > of each microarchitecture, with the appropriate compatible string to > > > > represent that (see the juno dts). > > > > > > You are right. The first version we wrote is: > > > pmu_a53 { > > > > > > compatible = "arm,cortex-a53-pmu"; > > > interrupts = ; > > > interrupt-affinity = <&cpu_l0>, > > > > > > <&cpu_l1>, > > > <&cpu_l2>, > > > <&cpu_l3>; > > > > > > }; > > > > > > pmu_a72 { > > > > > > compatible = "arm,cortex-a72-pmu"; > > > interrupts = ; > > > interrupt-affinity = <&cpu_b0>, > > > > > > <&cpu_b1>; > > > > > > }; > > > > > > but unfortunately, the arm pmu driver do not support PPI in two cluster > > > well, > > > so we have to replace with this implementation. > > > > > > > In this case things are messier as the same PPI number is being used > > > > across clusters. Marc (Cc'd) has been working on PPI partitions, which > > > > should allow us to support that. > > > > > > Great! So what we can do right now? Wait this feature, and delete > > > arm-pmu node? > > > > I'd rather you have a look at the patches, test them with your HW, > > and comment on what doesn't work! > > I would think we could do it in two tracks, testing and fixing but also letting > the rk3399 devicetrees move forward without the pmu at first :-) . Where would the fun be then? ;-) M. -- Jazz is not dead. It just smells funny.