Re: [for-4.7] xen/arm: Force broadcast of TLB and instruction cache maintenance instructions

[Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>]

On Mon, Apr 18, 2016 at 10:29:51AM +0100, Julien Grall wrote:
> UP guest usually uses TLB instruction to flush only on the local CPU. The
> TLB flush won't be broadcasted across all the CPUs within the same
> innershareable domain.
> 
> When the vCPU is migrated between different CPUs, it may be rescheduled
> to a previous CPU where the TLB has not been flushed. The TLB may
> contain stale entries which will result to translate incorrectly a VA to
> IPA or even cause TLB conflicts.
> 
> To avoid a such situation, always set HCR_EL2.FB which will force the
> broadcast of TLB and instruction cache maintenance instructions.
> Cheers,
> 
> Signed-off-by: Julien Grall <julien.grall@arm.com>

Hey!

I presume this needs an Release-Ack ?

> ---
> 
> This is a bug fix for Xen 4.7 and should be backported up to Xen 4.4
> (first official release for ARM). Without this patch, UP guest will
> crash if it gets migrated on a physical CPU with stale TLBs for this
> guest.
> ---
>  xen/arch/arm/traps.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> index 5e865cf..9926a57 100644
> --- a/xen/arch/arm/traps.c
> +++ b/xen/arch/arm/traps.c
> @@ -124,7 +124,8 @@ void init_traps(void)
>  
>      /* Setup hypervisor traps */
>      WRITE_SYSREG(HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM|
> -                 HCR_TWE|HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP, HCR_EL2);
> +                 HCR_TWE|HCR_TWI|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB,
> +                 HCR_EL2);
>      isb();
>  }
>  
> -- 
> 1.9.1
> 
> 
> _______________________________________________
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> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel

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