From: Stephen Boyd <sboyd@codeaurora.org>
To: Jiancheng Xue <xuejiancheng@hisilicon.com>
Cc: mturquette@baylibre.com, p.zabel@pengutronix.de,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, yanhaifeng@hisilicon.com,
yanghongwei@hisilicon.com, suwenping@hisilicon.com,
raojun@hisilicon.com, ml.yang@hisilicon.com,
gaofei@hisilicon.com, zhangzhenxing@hisilicon.com,
hermit.wangheming@hisilicon.com, jiangheng@hisilicon.com
Subject: Re: [PATCH 1/3] reset: hisilicon: add reset controller driver for hisilicon SOCs
Date: Fri, 6 May 2016 11:20:20 -0700 [thread overview]
Message-ID: <20160506182020.GC3492@codeaurora.org> (raw)
In-Reply-To: <1461397230-1757-2-git-send-email-xuejiancheng@hisilicon.com>
On 04/23, Jiancheng Xue wrote:
> In most of hisilicon SOCs, reset controller and clock provider are
> combined together as a block named CRG (Clock and Reset Generator).
> This patch mainly implements the reset function.
>
> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
Applied to clk-hi3519
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-05-06 18:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-23 7:40 [PATCH 0/3] clock: hisilicon: Add CRG driver for hi3519 soc Jiancheng Xue
2016-04-23 7:40 ` [PATCH 1/3] reset: hisilicon: add reset controller driver for hisilicon SOCs Jiancheng Xue
2016-05-06 18:20 ` Stephen Boyd [this message]
2016-04-23 7:40 ` [PATCH 2/3] clk: hisilicon: export some hisilicon APIs to modules Jiancheng Xue
2016-05-06 18:20 ` Stephen Boyd
2016-04-23 7:40 ` [PATCH 3/3] clk: hisilicon: add CRG driver for hi3519 soc Jiancheng Xue
2016-05-06 18:19 ` Stephen Boyd
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