diff for duplicates of <20160509160215.GF19473@dell> diff --git a/a/1.txt b/N1/1.txt index 9ec9463..ccde186 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,16 +1,17 @@ -On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote: +On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote: -> From: Thor Thayer <tthayer@opensource.altera.com> +> From: Thor Thayer <ttha...@opensource.altera.com> > > Add support for the Altera Arria10 Development Kit System Resource > chip which is implemented using a MAX5 as a external gpio extender, > and power supply alarm (hwmon) with the regmap framework over a SPI bus. > -> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> +> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com> > --- > drivers/mfd/Kconfig | 11 +++ > drivers/mfd/Makefile | 2 + -> drivers/mfd/altera-a10sr.c | 179 ++++++++++++++++++++++++++++++++++++++ +> drivers/mfd/altera-a10sr.c | 179 +> ++++++++++++++++++++++++++++++++++++++ > include/linux/mfd/altera-a10sr.h | 87 ++++++++++++++++++ > 4 files changed, 279 insertions(+) > create mode 100644 drivers/mfd/altera-a10sr.c @@ -21,7 +22,7 @@ On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote: > --- a/drivers/mfd/Kconfig > +++ b/drivers/mfd/Kconfig > @@ -18,6 +18,17 @@ config MFD_CS5535 -> This is the core driver for CS5535/CS5536 MFD functions. This is +> This is the core driver for CS5535/CS5536 MFD functions. This is > necessary for using the board's GPIO and MFGPT functionality. > > +config MFD_ALTERA_A10SR @@ -36,18 +37,19 @@ On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote: > + power supply alarms (hwmon). > + > config MFD_ACT8945A -> tristate "Active-semi ACT8945A" -> select MFD_CORE +> tristate "Active-semi ACT8945A" +> select MFD_CORE > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > index 5eaa6465d..4f1ff91 100644 > --- a/drivers/mfd/Makefile > +++ b/drivers/mfd/Makefile -> @@ -203,3 +203,5 @@ intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o -> intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o -> obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o -> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o +> @@ -203,3 +203,5 @@ intel-soc-pmic-objs := +> intel_soc_pmic_core.o intel_soc_pmic_crc.o +> intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o +> obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o +> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o > + -> +obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o +> +obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o > diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c > new file mode 100644 > index 0000000..2ff08e3 @@ -66,14 +68,15 @@ On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote: > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * -> + * You should have received a copy of the GNU General Public License along with +> + * You should have received a copy of the GNU General Public License along +> with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + * > + * SPI access for Altera Arria10 MAX5 System Resource Chip > + * > + * Adapted from DA9052 > + * Copyright(c) 2011 Dialog Semiconductor Ltd. -> + * Author: David Dajun Chen <dchen@diasemi.com> +> + * Author: David Dajun Chen <dc...@diasemi.com> You don't need to carry the copyright or authorship tags over. @@ -86,164 +89,165 @@ You don't need to carry the copyright or authorship tags over. > +#include <linux/spi/spi.h> > + > +static const struct mfd_cell altr_a10sr_subdev_info[] = { -> + { -> + .name = "altr_a10sr_gpio", -> + .of_compatible = "altr,a10sr-gpio", -> + }, +> + { +> + .name = "altr_a10sr_gpio", +> + .of_compatible = "altr,a10sr-gpio", +> + }, > +}; > + > +static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg) > +{ -> + switch (reg) { -> + case ALTR_A10SR_VERSION_READ: -> + case ALTR_A10SR_LED_REG: -> + case ALTR_A10SR_PBDSW_REG: -> + case ALTR_A10SR_PBDSW_IRQ_REG: -> + case ALTR_A10SR_PWR_GOOD1_REG: -> + case ALTR_A10SR_PWR_GOOD2_REG: -> + case ALTR_A10SR_PWR_GOOD3_REG: -> + case ALTR_A10SR_FMCAB_REG: -> + case ALTR_A10SR_HPS_RST_REG: -> + case ALTR_A10SR_USB_QSPI_REG: -> + case ALTR_A10SR_SFPA_REG: -> + case ALTR_A10SR_SFPB_REG: -> + case ALTR_A10SR_I2C_M_REG: -> + case ALTR_A10SR_WARM_RST_REG: -> + case ALTR_A10SR_WR_KEY_REG: -> + case ALTR_A10SR_PMBUS_REG: -> + return true; -> + default: -> + return false; -> + } +> + switch (reg) { +> + case ALTR_A10SR_VERSION_READ: +> + case ALTR_A10SR_LED_REG: +> + case ALTR_A10SR_PBDSW_REG: +> + case ALTR_A10SR_PBDSW_IRQ_REG: +> + case ALTR_A10SR_PWR_GOOD1_REG: +> + case ALTR_A10SR_PWR_GOOD2_REG: +> + case ALTR_A10SR_PWR_GOOD3_REG: +> + case ALTR_A10SR_FMCAB_REG: +> + case ALTR_A10SR_HPS_RST_REG: +> + case ALTR_A10SR_USB_QSPI_REG: +> + case ALTR_A10SR_SFPA_REG: +> + case ALTR_A10SR_SFPB_REG: +> + case ALTR_A10SR_I2C_M_REG: +> + case ALTR_A10SR_WARM_RST_REG: +> + case ALTR_A10SR_WR_KEY_REG: +> + case ALTR_A10SR_PMBUS_REG: +> + return true; +> + default: +> + return false; +> + } > +} > + > +static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg) > +{ -> + switch (reg) { -> + case ALTR_A10SR_LED_REG: -> + case ALTR_A10SR_PBDSW_IRQ_REG: -> + case ALTR_A10SR_FMCAB_REG: -> + case ALTR_A10SR_HPS_RST_REG: -> + case ALTR_A10SR_USB_QSPI_REG: -> + case ALTR_A10SR_SFPA_REG: -> + case ALTR_A10SR_SFPB_REG: -> + case ALTR_A10SR_WARM_RST_REG: -> + case ALTR_A10SR_WR_KEY_REG: -> + case ALTR_A10SR_PMBUS_REG: -> + return true; -> + default: -> + return false; -> + } +> + switch (reg) { +> + case ALTR_A10SR_LED_REG: +> + case ALTR_A10SR_PBDSW_IRQ_REG: +> + case ALTR_A10SR_FMCAB_REG: +> + case ALTR_A10SR_HPS_RST_REG: +> + case ALTR_A10SR_USB_QSPI_REG: +> + case ALTR_A10SR_SFPA_REG: +> + case ALTR_A10SR_SFPB_REG: +> + case ALTR_A10SR_WARM_RST_REG: +> + case ALTR_A10SR_WR_KEY_REG: +> + case ALTR_A10SR_PMBUS_REG: +> + return true; +> + default: +> + return false; +> + } > +} > + > +static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg) > +{ -> + switch (reg) { -> + case ALTR_A10SR_PBDSW_REG: -> + case ALTR_A10SR_PBDSW_IRQ_REG: -> + case ALTR_A10SR_PWR_GOOD1_REG: -> + case ALTR_A10SR_PWR_GOOD2_REG: -> + case ALTR_A10SR_PWR_GOOD3_REG: -> + case ALTR_A10SR_HPS_RST_REG: -> + case ALTR_A10SR_I2C_M_REG: -> + case ALTR_A10SR_WARM_RST_REG: -> + case ALTR_A10SR_WR_KEY_REG: -> + case ALTR_A10SR_PMBUS_REG: -> + return true; -> + default: -> + return false; -> + } +> + switch (reg) { +> + case ALTR_A10SR_PBDSW_REG: +> + case ALTR_A10SR_PBDSW_IRQ_REG: +> + case ALTR_A10SR_PWR_GOOD1_REG: +> + case ALTR_A10SR_PWR_GOOD2_REG: +> + case ALTR_A10SR_PWR_GOOD3_REG: +> + case ALTR_A10SR_HPS_RST_REG: +> + case ALTR_A10SR_I2C_M_REG: +> + case ALTR_A10SR_WARM_RST_REG: +> + case ALTR_A10SR_WR_KEY_REG: +> + case ALTR_A10SR_PMBUS_REG: +> + return true; +> + default: +> + return false; +> + } > +} > + > +const struct regmap_config altr_a10sr_regmap_config = { -> + .reg_bits = 8, -> + .val_bits = 8, +> + .reg_bits = 8, +> + .val_bits = 8, > + -> + .cache_type = REGCACHE_NONE, +> + .cache_type = REGCACHE_NONE, > + -> + .use_single_rw = true, -> + .read_flag_mask = 1, -> + .write_flag_mask = 0, +> + .use_single_rw = true, +> + .read_flag_mask = 1, +> + .write_flag_mask = 0, > + -> + .max_register = ALTR_A10SR_WR_KEY_REG, -> + .readable_reg = altr_a10sr_reg_readable, -> + .writeable_reg = altr_a10sr_reg_writeable, -> + .volatile_reg = altr_a10sr_reg_volatile, +> + .max_register = ALTR_A10SR_WR_KEY_REG, +> + .readable_reg = altr_a10sr_reg_readable, +> + .writeable_reg = altr_a10sr_reg_writeable, +> + .volatile_reg = altr_a10sr_reg_volatile, > + > +}; > + > +static int altr_a10sr_spi_probe(struct spi_device *spi) > +{ -> + int ret; -> + struct altr_a10sr *a10sr; +> + int ret; +> + struct altr_a10sr *a10sr; > + -> + a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr), -> + GFP_KERNEL); -> + if (!a10sr) -> + return -ENOMEM; +> + a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr), +> + GFP_KERNEL); +> + if (!a10sr) +> + return -ENOMEM; > + -> + spi->mode = SPI_MODE_3; -> + spi->bits_per_word = 8; -> + spi_setup(spi); +> + spi->mode = SPI_MODE_3; +> + spi->bits_per_word = 8; +> + spi_setup(spi); > + -> + a10sr->dev = &spi->dev; +> + a10sr->dev = &spi->dev; > + -> + spi_set_drvdata(spi, a10sr); +> + spi_set_drvdata(spi, a10sr); > + -> + a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config); -> + if (IS_ERR(a10sr->regmap)) { -> + ret = PTR_ERR(a10sr->regmap); -> + dev_err(&spi->dev, "Failed to allocate register map: %d\n", -> + ret); -> + return ret; -> + } +> + a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config); +> + if (IS_ERR(a10sr->regmap)) { +> + ret = PTR_ERR(a10sr->regmap); +> + dev_err(&spi->dev, "Failed to allocate register map: %d\n", +> + ret); +> + return ret; +> + } Is this regmap used it more than one driver? -> + ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO, -> + altr_a10sr_subdev_info, -> + ARRAY_SIZE(altr_a10sr_subdev_info), -> + NULL, 0, NULL); -> + if (ret) -> + dev_err(a10sr->dev, "Failed to register sub-devices: %d\n", -> + ret); -> + -> + return ret; +> + ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO, +> + altr_a10sr_subdev_info, +> + ARRAY_SIZE(altr_a10sr_subdev_info), +> + NULL, 0, NULL); +> + if (ret) +> + dev_err(a10sr->dev, "Failed to register sub-devices: %d\n", +> + ret); +> + +> + return ret; > +} > + > +static int altr_a10sr_spi_remove(struct spi_device *spi) > +{ -> + mfd_remove_devices(&spi->dev); +> + mfd_remove_devices(&spi->dev); > + -> + return 0; +> + return 0; > +} Use devm_mfd_add_devices() and remove this function. > +static const struct of_device_id altr_a10sr_spi_of_match[] = { -> + { .compatible = "altr,a10sr" }, -> + { }, +> + { .compatible = "altr,a10sr" }, +> + { }, > +}; > +MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match); > + > +static struct spi_driver altr_a10sr_spi_driver = { -> + .probe = altr_a10sr_spi_probe, -> + .remove = altr_a10sr_spi_remove, +> + .probe = altr_a10sr_spi_probe, +> + .remove = altr_a10sr_spi_remove, Remove .remove. -> + .driver = { -> + .name = "altr_a10sr", -> + .of_match_table = of_match_ptr(altr_a10sr_spi_of_match), -> + }, +> + .driver = { +> + .name = "altr_a10sr", +> + .of_match_table = of_match_ptr(altr_a10sr_spi_of_match), +> + }, > +}; > + > +module_spi_driver(altr_a10sr_spi_driver); > + > +MODULE_LICENSE("GPL v2"); -> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>"); +> +MODULE_AUTHOR("Thor Thayer <ttha...@opensource.altera.com>"); > +MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver"); -> diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h +> diff --git a/include/linux/mfd/altera-a10sr.h +> b/include/linux/mfd/altera-a10sr.h > new file mode 100644 > index 0000000..c869fe7 > --- /dev/null @@ -261,14 +265,15 @@ Remove .remove. > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * -> + * You should have received a copy of the GNU General Public License along with +> + * You should have received a copy of the GNU General Public License along +> with > + * this program. If not, see <http://www.gnu.org/licenses/>. > + * > + * Declarations for Altera Arria10 MAX5 System Resource Chip > + * > + * Adapted from DA9052 > + * Copyright(c) 2011 Dialog Semiconductor Ltd. -> + * Author: David Dajun Chen <dchen@diasemi.com> +> + * Author: David Dajun Chen <dc...@diasemi.com> Remove these two lines. @@ -294,7 +299,8 @@ Remove these two lines. > + * the number of GPIO in each register. We then need to multiply > + * by 2 because the reads are at odd addresses. > + */ -> +#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1) +> +#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) +> << 1) > +#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER) > +#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y)) > +#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X)) @@ -305,7 +311,8 @@ Remove these two lines. > + > +#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */ > +/* LED register Bit Definitions */ -> +#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */ +> +#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits +> valid */ > +#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT > +#define ALTR_A10SR_OUT_VALID_RANGE_HI 7 > + @@ -334,8 +341,8 @@ Remove these two lines. > + * @regmap: the regmap assigned to the parent device. > + */ > +struct altr_a10sr { -> + struct device *dev; -> + struct regmap *regmap; +> + struct device *dev; +> + struct regmap *regmap; > +}; > + > +#endif /* __MFD_ALTERA_A10SR_H */ @@ -343,9 +350,9 @@ Remove these two lines. -- Lee Jones Linaro STMicroelectronics Landing Team Lead -Linaro.org │ Open source software for ARM SoCs +Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- -To unsubscribe from this list: send the line "unsubscribe linux-gpio" in -the body of a message to majordomo@vger.kernel.org +To unsubscribe from this list: send the line "unsubscribe linux-hwmon" in +the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index c9b8d4e..27863c8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,36 +1,24 @@ "ref\01461339219-15255-1-git-send-email-tthayer@opensource.altera.com\0" - "ref\01461339219-15255-4-git-send-email-tthayer@opensource.altera.com\0" "From\0Lee Jones <lee.jones@linaro.org>\0" "Subject\0Re: [PATCH 03/11] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip\0" - "Date\0Mon, 9 May 2016 17:02:15 +0100\0" - "To\0tthayer@opensource.altera.com\0" - "Cc\0linus.walleij@linaro.org" - gnurou@gmail.com - jdelvare@suse.com - linux@roeck-us.net - robh+dt@kernel.org - pawel.moll@arm.com - mark.rutland@arm.com - ijc+devicetree@hellion.org.uk - dinguyen@opensource.altera.com - linux-gpio@vger.kernel.org - linux-hwmon@vger.kernel.org - " devicetree@vger.kernel.org\0" + "Date\0Mon, 09 May 2016 09:02:34 -0700\0" + "To\0linux-hwmon@vger.kernel.org\0" "\00:1\0" "b\0" - "On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote:\n" + "On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote:\n" "\n" - "> From: Thor Thayer <tthayer@opensource.altera.com>\n" + "> From: Thor Thayer <ttha...@opensource.altera.com>\n" "> \n" "> Add support for the Altera Arria10 Development Kit System Resource\n" "> chip which is implemented using a MAX5 as a external gpio extender,\n" "> and power supply alarm (hwmon) with the regmap framework over a SPI bus.\n" "> \n" - "> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>\n" + "> Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>\n" "> ---\n" "> drivers/mfd/Kconfig | 11 +++\n" "> drivers/mfd/Makefile | 2 +\n" - "> drivers/mfd/altera-a10sr.c | 179 ++++++++++++++++++++++++++++++++++++++\n" + "> drivers/mfd/altera-a10sr.c | 179 \n" + "> ++++++++++++++++++++++++++++++++++++++\n" "> include/linux/mfd/altera-a10sr.h | 87 ++++++++++++++++++\n" "> 4 files changed, 279 insertions(+)\n" "> create mode 100644 drivers/mfd/altera-a10sr.c\n" @@ -41,7 +29,7 @@ "> --- a/drivers/mfd/Kconfig\n" "> +++ b/drivers/mfd/Kconfig\n" "> @@ -18,6 +18,17 @@ config MFD_CS5535\n" - "> \t This is the core driver for CS5535/CS5536 MFD functions. This is\n" + "> This is the core driver for CS5535/CS5536 MFD functions. This is\n" "> necessary for using the board's GPIO and MFGPT functionality.\n" "> \n" "> +config MFD_ALTERA_A10SR\n" @@ -56,18 +44,19 @@ "> + power supply alarms (hwmon).\n" "> +\n" "> config MFD_ACT8945A\n" - "> \ttristate \"Active-semi ACT8945A\"\n" - "> \tselect MFD_CORE\n" + "> tristate \"Active-semi ACT8945A\"\n" + "> select MFD_CORE\n" "> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile\n" "> index 5eaa6465d..4f1ff91 100644\n" "> --- a/drivers/mfd/Makefile\n" "> +++ b/drivers/mfd/Makefile\n" - "> @@ -203,3 +203,5 @@ intel-soc-pmic-objs\t\t:= intel_soc_pmic_core.o intel_soc_pmic_crc.o\n" - "> intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)\t+= intel_soc_pmic_bxtwc.o\n" - "> obj-$(CONFIG_INTEL_SOC_PMIC)\t+= intel-soc-pmic.o\n" - "> obj-$(CONFIG_MFD_MT6397)\t+= mt6397-core.o\n" + "> @@ -203,3 +203,5 @@ intel-soc-pmic-objs := \n" + "> intel_soc_pmic_core.o intel_soc_pmic_crc.o\n" + "> intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o\n" + "> obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o\n" + "> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o\n" "> +\n" - "> +obj-$(CONFIG_MFD_ALTERA_A10SR)\t+= altera-a10sr.o\n" + "> +obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o\n" "> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c\n" "> new file mode 100644\n" "> index 0000000..2ff08e3\n" @@ -86,14 +75,15 @@ "> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n" "> + * more details.\n" "> + *\n" - "> + * You should have received a copy of the GNU General Public License along with\n" + "> + * You should have received a copy of the GNU General Public License along \n" + "> with\n" "> + * this program. If not, see <http://www.gnu.org/licenses/>.\n" "> + *\n" "> + * SPI access for Altera Arria10 MAX5 System Resource Chip\n" "> + *\n" "> + * Adapted from DA9052\n" "> + * Copyright(c) 2011 Dialog Semiconductor Ltd.\n" - "> + * Author: David Dajun Chen <dchen@diasemi.com>\n" + "> + * Author: David Dajun Chen <dc...@diasemi.com>\n" "\n" "You don't need to carry the copyright or authorship tags over.\n" "\n" @@ -106,164 +96,165 @@ "> +#include <linux/spi/spi.h>\n" "> +\n" "> +static const struct mfd_cell altr_a10sr_subdev_info[] = {\n" - "> +\t{\n" - "> +\t\t.name = \"altr_a10sr_gpio\",\n" - "> +\t\t.of_compatible = \"altr,a10sr-gpio\",\n" - "> +\t},\n" + "> + {\n" + "> + .name = \"altr_a10sr_gpio\",\n" + "> + .of_compatible = \"altr,a10sr-gpio\",\n" + "> + },\n" "> +};\n" "> +\n" "> +static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)\n" "> +{\n" - "> +\tswitch (reg) {\n" - "> +\tcase ALTR_A10SR_VERSION_READ:\n" - "> +\tcase ALTR_A10SR_LED_REG:\n" - "> +\tcase ALTR_A10SR_PBDSW_REG:\n" - "> +\tcase ALTR_A10SR_PBDSW_IRQ_REG:\n" - "> +\tcase ALTR_A10SR_PWR_GOOD1_REG:\n" - "> +\tcase ALTR_A10SR_PWR_GOOD2_REG:\n" - "> +\tcase ALTR_A10SR_PWR_GOOD3_REG:\n" - "> +\tcase ALTR_A10SR_FMCAB_REG:\n" - "> +\tcase ALTR_A10SR_HPS_RST_REG:\n" - "> +\tcase ALTR_A10SR_USB_QSPI_REG:\n" - "> +\tcase ALTR_A10SR_SFPA_REG:\n" - "> +\tcase ALTR_A10SR_SFPB_REG:\n" - "> +\tcase ALTR_A10SR_I2C_M_REG:\n" - "> +\tcase ALTR_A10SR_WARM_RST_REG:\n" - "> +\tcase ALTR_A10SR_WR_KEY_REG:\n" - "> +\tcase ALTR_A10SR_PMBUS_REG:\n" - "> +\t\treturn true;\n" - "> +\tdefault:\n" - "> +\t\treturn false;\n" - "> +\t}\n" + "> + switch (reg) {\n" + "> + case ALTR_A10SR_VERSION_READ:\n" + "> + case ALTR_A10SR_LED_REG:\n" + "> + case ALTR_A10SR_PBDSW_REG:\n" + "> + case ALTR_A10SR_PBDSW_IRQ_REG:\n" + "> + case ALTR_A10SR_PWR_GOOD1_REG:\n" + "> + case ALTR_A10SR_PWR_GOOD2_REG:\n" + "> + case ALTR_A10SR_PWR_GOOD3_REG:\n" + "> + case ALTR_A10SR_FMCAB_REG:\n" + "> + case ALTR_A10SR_HPS_RST_REG:\n" + "> + case ALTR_A10SR_USB_QSPI_REG:\n" + "> + case ALTR_A10SR_SFPA_REG:\n" + "> + case ALTR_A10SR_SFPB_REG:\n" + "> + case ALTR_A10SR_I2C_M_REG:\n" + "> + case ALTR_A10SR_WARM_RST_REG:\n" + "> + case ALTR_A10SR_WR_KEY_REG:\n" + "> + case ALTR_A10SR_PMBUS_REG:\n" + "> + return true;\n" + "> + default:\n" + "> + return false;\n" + "> + }\n" "> +}\n" "> +\n" "> +static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)\n" "> +{\n" - "> +\tswitch (reg) {\n" - "> +\tcase ALTR_A10SR_LED_REG:\n" - "> +\tcase ALTR_A10SR_PBDSW_IRQ_REG:\n" - "> +\tcase ALTR_A10SR_FMCAB_REG:\n" - "> +\tcase ALTR_A10SR_HPS_RST_REG:\n" - "> +\tcase ALTR_A10SR_USB_QSPI_REG:\n" - "> +\tcase ALTR_A10SR_SFPA_REG:\n" - "> +\tcase ALTR_A10SR_SFPB_REG:\n" - "> +\tcase ALTR_A10SR_WARM_RST_REG:\n" - "> +\tcase ALTR_A10SR_WR_KEY_REG:\n" - "> +\tcase ALTR_A10SR_PMBUS_REG:\n" - "> +\t\treturn true;\n" - "> +\tdefault:\n" - "> +\t\treturn false;\n" - "> +\t}\n" + "> + switch (reg) {\n" + "> + case ALTR_A10SR_LED_REG:\n" + "> + case ALTR_A10SR_PBDSW_IRQ_REG:\n" + "> + case ALTR_A10SR_FMCAB_REG:\n" + "> + case ALTR_A10SR_HPS_RST_REG:\n" + "> + case ALTR_A10SR_USB_QSPI_REG:\n" + "> + case ALTR_A10SR_SFPA_REG:\n" + "> + case ALTR_A10SR_SFPB_REG:\n" + "> + case ALTR_A10SR_WARM_RST_REG:\n" + "> + case ALTR_A10SR_WR_KEY_REG:\n" + "> + case ALTR_A10SR_PMBUS_REG:\n" + "> + return true;\n" + "> + default:\n" + "> + return false;\n" + "> + }\n" "> +}\n" "> +\n" "> +static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)\n" "> +{\n" - "> +\tswitch (reg) {\n" - "> +\tcase ALTR_A10SR_PBDSW_REG:\n" - "> +\tcase ALTR_A10SR_PBDSW_IRQ_REG:\n" - "> +\tcase ALTR_A10SR_PWR_GOOD1_REG:\n" - "> +\tcase ALTR_A10SR_PWR_GOOD2_REG:\n" - "> +\tcase ALTR_A10SR_PWR_GOOD3_REG:\n" - "> +\tcase ALTR_A10SR_HPS_RST_REG:\n" - "> +\tcase ALTR_A10SR_I2C_M_REG:\n" - "> +\tcase ALTR_A10SR_WARM_RST_REG:\n" - "> +\tcase ALTR_A10SR_WR_KEY_REG:\n" - "> +\tcase ALTR_A10SR_PMBUS_REG:\n" - "> +\t\treturn true;\n" - "> +\tdefault:\n" - "> +\t\treturn false;\n" - "> +\t}\n" + "> + switch (reg) {\n" + "> + case ALTR_A10SR_PBDSW_REG:\n" + "> + case ALTR_A10SR_PBDSW_IRQ_REG:\n" + "> + case ALTR_A10SR_PWR_GOOD1_REG:\n" + "> + case ALTR_A10SR_PWR_GOOD2_REG:\n" + "> + case ALTR_A10SR_PWR_GOOD3_REG:\n" + "> + case ALTR_A10SR_HPS_RST_REG:\n" + "> + case ALTR_A10SR_I2C_M_REG:\n" + "> + case ALTR_A10SR_WARM_RST_REG:\n" + "> + case ALTR_A10SR_WR_KEY_REG:\n" + "> + case ALTR_A10SR_PMBUS_REG:\n" + "> + return true;\n" + "> + default:\n" + "> + return false;\n" + "> + }\n" "> +}\n" "> +\n" "> +const struct regmap_config altr_a10sr_regmap_config = {\n" - "> +\t.reg_bits = 8,\n" - "> +\t.val_bits = 8,\n" + "> + .reg_bits = 8,\n" + "> + .val_bits = 8,\n" "> +\n" - "> +\t.cache_type = REGCACHE_NONE,\n" + "> + .cache_type = REGCACHE_NONE,\n" "> +\n" - "> +\t.use_single_rw = true,\n" - "> +\t.read_flag_mask = 1,\n" - "> +\t.write_flag_mask = 0,\n" + "> + .use_single_rw = true,\n" + "> + .read_flag_mask = 1,\n" + "> + .write_flag_mask = 0,\n" "> +\n" - "> +\t.max_register = ALTR_A10SR_WR_KEY_REG,\n" - "> +\t.readable_reg = altr_a10sr_reg_readable,\n" - "> +\t.writeable_reg = altr_a10sr_reg_writeable,\n" - "> +\t.volatile_reg = altr_a10sr_reg_volatile,\n" + "> + .max_register = ALTR_A10SR_WR_KEY_REG,\n" + "> + .readable_reg = altr_a10sr_reg_readable,\n" + "> + .writeable_reg = altr_a10sr_reg_writeable,\n" + "> + .volatile_reg = altr_a10sr_reg_volatile,\n" "> +\n" "> +};\n" "> +\n" "> +static int altr_a10sr_spi_probe(struct spi_device *spi)\n" "> +{\n" - "> +\tint ret;\n" - "> +\tstruct altr_a10sr *a10sr;\n" + "> + int ret;\n" + "> + struct altr_a10sr *a10sr;\n" "> +\n" - "> +\ta10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),\n" - "> +\t\t\t GFP_KERNEL);\n" - "> +\tif (!a10sr)\n" - "> +\t\treturn -ENOMEM;\n" + "> + a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),\n" + "> + GFP_KERNEL);\n" + "> + if (!a10sr)\n" + "> + return -ENOMEM;\n" "> +\n" - "> +\tspi->mode = SPI_MODE_3;\n" - "> +\tspi->bits_per_word = 8;\n" - "> +\tspi_setup(spi);\n" + "> + spi->mode = SPI_MODE_3;\n" + "> + spi->bits_per_word = 8;\n" + "> + spi_setup(spi);\n" "> +\n" - "> +\ta10sr->dev = &spi->dev;\n" + "> + a10sr->dev = &spi->dev;\n" "> +\n" - "> +\tspi_set_drvdata(spi, a10sr);\n" + "> + spi_set_drvdata(spi, a10sr);\n" "> +\n" - "> +\ta10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);\n" - "> +\tif (IS_ERR(a10sr->regmap)) {\n" - "> +\t\tret = PTR_ERR(a10sr->regmap);\n" - "> +\t\tdev_err(&spi->dev, \"Failed to allocate register map: %d\\n\",\n" - "> +\t\t\tret);\n" - "> +\t\treturn ret;\n" - "> +\t}\n" + "> + a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);\n" + "> + if (IS_ERR(a10sr->regmap)) {\n" + "> + ret = PTR_ERR(a10sr->regmap);\n" + "> + dev_err(&spi->dev, \"Failed to allocate register map: %d\\n\",\n" + "> + ret);\n" + "> + return ret;\n" + "> + }\n" "\n" "Is this regmap used it more than one driver?\n" "\n" - "> +\tret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,\n" - "> +\t\t\t altr_a10sr_subdev_info,\n" - "> +\t\t\t ARRAY_SIZE(altr_a10sr_subdev_info),\n" - "> +\t\t\t NULL, 0, NULL);\n" - "> +\tif (ret)\n" - "> +\t\tdev_err(a10sr->dev, \"Failed to register sub-devices: %d\\n\",\n" - "> +\t\t\tret);\n" - "> +\n" - "> +\treturn ret;\n" + "> + ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,\n" + "> + altr_a10sr_subdev_info,\n" + "> + ARRAY_SIZE(altr_a10sr_subdev_info),\n" + "> + NULL, 0, NULL);\n" + "> + if (ret)\n" + "> + dev_err(a10sr->dev, \"Failed to register sub-devices: %d\\n\",\n" + "> + ret);\n" + "> +\n" + "> + return ret;\n" "> +}\n" "> +\n" "> +static int altr_a10sr_spi_remove(struct spi_device *spi)\n" "> +{\n" - "> +\tmfd_remove_devices(&spi->dev);\n" + "> + mfd_remove_devices(&spi->dev);\n" "> +\n" - "> +\treturn 0;\n" + "> + return 0;\n" "> +}\n" "\n" "Use devm_mfd_add_devices() and remove this function.\n" "\n" "> +static const struct of_device_id altr_a10sr_spi_of_match[] = {\n" - "> +\t{ .compatible = \"altr,a10sr\" },\n" - "> +\t{ },\n" + "> + { .compatible = \"altr,a10sr\" },\n" + "> + { },\n" "> +};\n" "> +MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);\n" "> +\n" "> +static struct spi_driver altr_a10sr_spi_driver = {\n" - "> +\t.probe = altr_a10sr_spi_probe,\n" - "> +\t.remove = altr_a10sr_spi_remove,\n" + "> + .probe = altr_a10sr_spi_probe,\n" + "> + .remove = altr_a10sr_spi_remove,\n" "\n" "Remove .remove.\n" "\n" - "> +\t.driver = {\n" - "> +\t\t.name = \"altr_a10sr\",\n" - "> +\t\t.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),\n" - "> +\t},\n" + "> + .driver = {\n" + "> + .name = \"altr_a10sr\",\n" + "> + .of_match_table = of_match_ptr(altr_a10sr_spi_of_match),\n" + "> + },\n" "> +};\n" "> +\n" "> +module_spi_driver(altr_a10sr_spi_driver);\n" "> +\n" "> +MODULE_LICENSE(\"GPL v2\");\n" - "> +MODULE_AUTHOR(\"Thor Thayer <tthayer@opensource.altera.com>\");\n" + "> +MODULE_AUTHOR(\"Thor Thayer <ttha...@opensource.altera.com>\");\n" "> +MODULE_DESCRIPTION(\"Altera Arria10 DevKit System Resource MFD Driver\");\n" - "> diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h\n" + "> diff --git a/include/linux/mfd/altera-a10sr.h \n" + "> b/include/linux/mfd/altera-a10sr.h\n" "> new file mode 100644\n" "> index 0000000..c869fe7\n" "> --- /dev/null\n" @@ -281,14 +272,15 @@ "> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n" "> + * more details.\n" "> + *\n" - "> + * You should have received a copy of the GNU General Public License along with\n" + "> + * You should have received a copy of the GNU General Public License along \n" + "> with\n" "> + * this program. If not, see <http://www.gnu.org/licenses/>.\n" "> + *\n" "> + * Declarations for Altera Arria10 MAX5 System Resource Chip\n" "> + *\n" "> + * Adapted from DA9052\n" "> + * Copyright(c) 2011 Dialog Semiconductor Ltd.\n" - "> + * Author: David Dajun Chen <dchen@diasemi.com>\n" + "> + * Author: David Dajun Chen <dc...@diasemi.com>\n" "\n" "Remove these two lines.\n" "\n" @@ -314,7 +306,8 @@ "> + * the number of GPIO in each register. We then need to multiply\n" "> + * by 2 because the reads are at odd addresses.\n" "> + */\n" - "> +#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)\n" + "> +#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) \n" + "> << 1)\n" "> +#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER)\n" "> +#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))\n" "> +#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X))\n" @@ -325,7 +318,8 @@ "> +\n" "> +#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */\n" "> +/* LED register Bit Definitions */\n" - "> +#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */\n" + "> +#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits \n" + "> valid */\n" "> +#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT\n" "> +#define ALTR_A10SR_OUT_VALID_RANGE_HI 7\n" "> +\n" @@ -354,8 +348,8 @@ "> + * @regmap: the regmap assigned to the parent device.\n" "> + */\n" "> +struct altr_a10sr {\n" - "> +\tstruct device *dev;\n" - "> +\tstruct regmap *regmap;\n" + "> + struct device *dev;\n" + "> + struct regmap *regmap;\n" "> +};\n" "> +\n" "> +#endif /* __MFD_ALTERA_A10SR_H */\n" @@ -363,11 +357,11 @@ "-- \n" "Lee Jones\n" "Linaro STMicroelectronics Landing Team Lead\n" - "Linaro.org \342\224\202 Open source software for ARM SoCs\n" + "Linaro.org \303\242\302\224\302\202 Open source software for ARM SoCs\n" "Follow Linaro: Facebook | Twitter | Blog\n" "--\n" - "To unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\n" - "the body of a message to majordomo@vger.kernel.org\n" + "To unsubscribe from this list: send the line \"unsubscribe linux-hwmon\" in\n" + "the body of a message to majord...@vger.kernel.org\n" More majordomo info at http://vger.kernel.org/majordomo-info.html -cb4966db2302086c8dc19561e78e4f5fa03f50f6594decfd8c6d4fc673257da1 +eefa75d240e7a9f37eca14a8a5c2b63a18dceeace0cafd7db13b490f944106ac
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.