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Date:   Fri, 20 May 2016 14:49:18 +0200
From:   Alban <albeu@free.fr>
To:     Felix Fietkau <nbd@nbd.name>
Cc:     Aban Bedel <albeu@free.fr>, linux-mips@linux-mips.org,
        sergei.shtylyov@cogentembedded.com
Subject: Re: [PATCH v2 1/2] MIPS: ath79: make ath79_ddr_ctrl_init()
 compatible for newer SoCs
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On Mon, 16 May 2016 19:51:54 +0200
Felix Fietkau <nbd@nbd.name> wrote:

> AR913x, AR724x and AR933x are the only SoCs where the
> ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c
> Invert the logic to make the code compatible with AR95xx
>=20
> Signed-off-by: Felix Fietkau <nbd@nbd.name>

Acked-by: Aban Bedel <albeu@free.fr>

Alban

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