From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Ro.CI.BAT: failure for drm/i915: SKL/KBL/BXT cdclk stuff
Date: Mon, 23 May 2016 20:25:15 +0300 [thread overview]
Message-ID: <20160523172515.GT4329@intel.com> (raw)
In-Reply-To: <20160514052557.10636.48880@emeril.freedesktop.org>
On Sat, May 14, 2016 at 05:25:57AM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: SKL/KBL/BXT cdclk stuff
> URL : https://patchwork.freedesktop.org/series/7169/
> State : failure
>
> == Summary ==
>
> Series 7169v1 drm/i915: SKL/KBL/BXT cdclk stuff
> http://patchwork.freedesktop.org/api/1.0/series/7169/revisions/1/mbox
>
> Test gem_exec_flush:
> Subgroup basic-batch-kernel-default-cmd:
> fail -> PASS (ro-byt-n2820)
> Test kms_flip:
> Subgroup basic-flip-vs-wf_vblank:
> pass -> FAIL (ro-hsw-i3-4010u)
(kms_flip:8003) DEBUG: name = vblank
last_ts = 626.544176 usec
last_received_ts = 626.543125 usec
last_seq = 623
current_ts = 626.877510 usec
current_received_ts = 626.876400 usec
current_seq = 633
count = 9
seq_step = 10
(kms_flip:8003) CRITICAL: Test assertion failure function check_final_state, file kms_flip.c:1192:
(kms_flip:8003) CRITICAL: Failed assertion: count >= expected * 99/100 && count <= expected * 101/100
(kms_flip:8003) CRITICAL: Last errno: 25, Inappropriate ioctl for device
(kms_flip:8003) CRITICAL: dropped frames, expected 99, counted 100, encoder type 2
https://bugs.freedesktop.org/show_bug.cgi?id=95380
> Test kms_pipe_crc_basic:
> Subgroup hang-read-crc-pipe-a:
> pass -> DMESG-WARN (ro-ivb2-i7-3770)
[ 531.288533] WARNING: CPU: 7 PID: 7836 at drivers/gpu/drm/i915/intel_display.c:13623 intel_atomic_commit+0x13b6/0x1460 [i915]
[ 531.288534] pipe A vblank wait timed out
https://bugs.freedesktop.org/show_bug.cgi?id=95125
>
> ro-bdw-i5-5250u total:219 pass:181 dwarn:0 dfail:0 fail:0 skip:38
> ro-bdw-i7-5557U total:219 pass:206 dwarn:0 dfail:0 fail:0 skip:13
> ro-bdw-i7-5600u total:219 pass:187 dwarn:0 dfail:0 fail:0 skip:32
> ro-bsw-n3050 total:219 pass:175 dwarn:0 dfail:0 fail:2 skip:42
> ro-byt-n2820 total:218 pass:175 dwarn:0 dfail:0 fail:2 skip:41
> ro-hsw-i3-4010u total:218 pass:192 dwarn:0 dfail:0 fail:1 skip:25
> ro-hsw-i7-4770r total:219 pass:194 dwarn:0 dfail:0 fail:0 skip:25
> ro-ilk-i7-620lm total:219 pass:151 dwarn:0 dfail:0 fail:1 skip:67
> ro-ilk1-i5-650 total:214 pass:152 dwarn:0 dfail:0 fail:1 skip:61
> ro-ivb2-i7-3770 total:219 pass:186 dwarn:1 dfail:0 fail:0 skip:32
> ro-skl-i7-6700hq total:214 pass:190 dwarn:0 dfail:0 fail:0 skip:24
> ro-snb-i7-2620M total:219 pass:177 dwarn:0 dfail:0 fail:1 skip:41
> ro-ivb-i7-3770 failed to connect after reboot
>
> Results at /archive/results/CI_IGT_test/RO_Patchwork_900/
>
> 1a536db drm-intel-nightly: 2016y-05m-13d-21h-21m-06s UTC integration manifest
> b974b6b drm/i915: Set BXT cdclk to minimum initially
> c75fe510 drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check
> ef3fb6c drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco
> b8ee27d drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk
> 77095f2 drm/i915: Update cached cdclk state from broxton_init_cdclk()
> 7c27fe0 drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv
> 351a2e3 drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk()
> dabb9dd drm/i915: Store cdclk PLL reference clock under dev_priv
> 995467c drm/i915: Rename skl_vco_freq to cdclk_pll.vco
> 19f5564 drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL
> 3499324 drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit
> 75083d8 drm/i915: Unify SKL cdclk init paths
> 0b482fa drm/i915: Beef up skl_sanitize_cdclk() a bit
> 5fe223b drm/i915: Keep track of preferred cdclk vco frequency on SKL
> b878f36 drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL
> 8fbef2c drm/i915: Report the current DPLL0 vco on SKL/KBL
> 244d5cc drm/i915: Actually read out DPLL0 vco on skl from hardware
> 7d03efe drm/i915: Extract skl_calc_cdclk()
> e2cd537 drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()
> 732fab3 drm/i915/skl: SKL CDCLK change on modeset tracking VCO
> e53fa8e drm/i915: Fix BXT min_pixclk after state readout
--
Ville Syrjälä
Intel OTC
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next prev parent reply other threads:[~2016-05-23 17:25 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-13 20:41 [PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff ville.syrjala
2016-05-13 20:41 ` [PATCH 01/21] drm/i915: Fix BXT min_pixclk after state readout ville.syrjala
2016-05-17 18:09 ` Imre Deak
2016-05-17 18:21 ` Ville Syrjälä
2016-05-17 18:24 ` Imre Deak
2016-05-13 20:41 ` [PATCH 02/21] drm/i915/skl: SKL CDCLK change on modeset tracking VCO ville.syrjala
2016-05-19 9:08 ` Imre Deak
2016-05-19 9:18 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 03/21] drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config() ville.syrjala
2016-05-19 11:57 ` Imre Deak
2016-05-13 20:41 ` [PATCH 04/21] drm/i915: Extract skl_calc_cdclk() ville.syrjala
2016-05-19 12:02 ` Imre Deak
2016-05-13 20:41 ` [PATCH 05/21] drm/i915: Actually read out DPLL0 vco on skl from hardware ville.syrjala
2016-05-19 12:38 ` Imre Deak
2016-05-13 20:41 ` [PATCH 06/21] drm/i915: Report the current DPLL0 vco on SKL/KBL ville.syrjala
2016-05-19 12:40 ` Imre Deak
2016-05-13 20:41 ` [PATCH 07/21] drm/i915: Allow enable/disable of DPLL0 around cdclk changes on SKL ville.syrjala
2016-05-19 13:04 ` Imre Deak
2016-05-19 13:18 ` Ville Syrjälä
2016-05-19 13:39 ` Imre Deak
2016-05-13 20:41 ` [PATCH 08/21] drm/i915: Keep track of preferred cdclk vco frequency " ville.syrjala
2016-05-19 14:25 ` Imre Deak
2016-05-13 20:41 ` [PATCH 09/21] drm/i915: Beef up skl_sanitize_cdclk() a bit ville.syrjala
2016-05-19 14:30 ` Imre Deak
2016-05-13 20:41 ` [PATCH 10/21] drm/i915: Unify SKL cdclk init paths ville.syrjala
2016-05-19 15:43 ` Imre Deak
2016-05-23 18:20 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 11/21] drm/i915: Move SKL+ DBUF enable/disable to display core init/uninit ville.syrjala
2016-05-19 15:48 ` Imre Deak
2016-05-23 18:20 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 12/21] drm/i915: Make 308 and 671 MHz cdclks more accurate on SKL ville.syrjala
2016-05-19 16:03 ` Imre Deak
2016-05-13 20:41 ` [PATCH 13/21] drm/i915: Rename skl_vco_freq to cdclk_pll.vco ville.syrjala
2016-05-19 16:17 ` Imre Deak
2016-05-19 16:21 ` Ville Syrjälä
2016-05-13 20:41 ` [PATCH 14/21] drm/i915: Store cdclk PLL reference clock under dev_priv ville.syrjala
2016-05-19 17:00 ` Imre Deak
2016-05-13 20:41 ` [PATCH 15/21] drm/i915: Extract bxt DE PLL enable/disable from broxton_set_cdclk() ville.syrjala
2016-05-19 17:04 ` Imre Deak
2016-05-13 20:41 ` [PATCH 16/21] drm/i915: Store BXT DE PLL vco and ref clocks in dev_priv ville.syrjala
2016-05-19 18:43 ` Imre Deak
2016-05-13 20:41 ` [PATCH 17/21] drm/i915: Update cached cdclk state from broxton_init_cdclk() ville.syrjala
2016-05-19 18:46 ` Imre Deak
2016-05-13 20:41 ` [PATCH 18/21] drm/i915: Rewrite broxton_get_display_clock_speed() in terms of the DE PLL vco/refclk ville.syrjala
2016-05-19 19:05 ` Imre Deak
2016-05-13 20:41 ` [PATCH 19/21] drm/i915: Make bxt_set_cdclk() operate in terms of the current vs target DE PLL vco ville.syrjala
2016-05-19 19:40 ` Imre Deak
2016-05-13 20:41 ` [PATCH 20/21] drm/i915: Replace bxt_verify_cdclk_state() with a more generic cdclk check ville.syrjala
2016-05-19 19:41 ` Imre Deak
2016-05-13 20:41 ` [PATCH 21/21] drm/i915: Set BXT cdclk to minimum initially ville.syrjala
2016-05-19 19:45 ` Imre Deak
2016-05-14 5:25 ` ✗ Ro.CI.BAT: failure for drm/i915: SKL/KBL/BXT cdclk stuff Patchwork
2016-05-23 17:25 ` Ville Syrjälä [this message]
2016-05-16 13:59 ` [PATCH 22/21] drm/i915: Assert the dbuf is enabled when disabling DC5/6 ville.syrjala
2016-05-19 19:49 ` Imre Deak
2016-05-23 18:21 ` Ville Syrjälä
2016-05-23 18:21 ` [PATCH 00/21] drm/i915: SKL/KBL/BXT cdclk stuff Ville Syrjälä
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