From: Pranith Kumar <bobby.prani@gmail.com>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <rth@twiddle.net>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Sergey Fedorov" <serge.fdrv@gmail.com>,
"open list:i386 target" <qemu-devel@nongnu.org>
Subject: [Qemu-devel] [RFC PATCH 1/3] Introduce TCGOpcode for fence instruction
Date: Tue, 24 May 2016 13:18:54 -0400 [thread overview]
Message-ID: <20160524171856.1000-2-bobby.prani@gmail.com> (raw)
In-Reply-To: <20160524171856.1000-1-bobby.prani@gmail.com>
This commit introduces the TCGOpcode for fence instruction.
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
tcg/i386/tcg-target.inc.c | 4 ++++
tcg/tcg-opc.h | 2 ++
tcg/tcg.c | 2 ++
3 files changed, 8 insertions(+)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 8fd37f4..238fa10 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2114,6 +2114,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_fence:
+ break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2179,6 +2181,8 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
+ { INDEX_op_fence, { } },
+
#if TCG_TARGET_REG_BITS == 32
{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 6d0410c..4696cf1 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -42,6 +42,8 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
# define IMPL64 TCG_OPF_64BIT
#endif
+DEF(fence, 0, 0, 0, 0)
+
DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(setcond_i32, 1, 2, 1, 0)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index b46bf1a..b5a22ba 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2443,6 +2443,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
tcg_reg_alloc_call(s, op->callo, op->calli, args,
dead_args, sync_args);
break;
+ case INDEX_op_fence:
+ break;
default:
/* Sanity check that we've not introduced any unhandled opcodes. */
if (def->flags & TCG_OPF_NOT_PRESENT) {
--
2.8.3
next parent reply other threads:[~2016-05-24 17:19 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20160524171856.1000-1-bobby.prani@gmail.com>
2016-05-24 17:18 ` Pranith Kumar [this message]
2016-05-24 17:32 ` [Qemu-devel] [RFC PATCH 1/3] Introduce TCGOpcode for fence instruction Peter Maydell
2016-05-24 18:05 ` Pranith Kumar
2016-05-24 17:18 ` [Qemu-devel] [RFC PATCH 2/3] tcg: Add support for fence generation in x86 backend Pranith Kumar
2016-05-25 17:35 ` Richard Henderson
2016-05-25 19:25 ` Alex Bennée
2016-05-25 19:43 ` Sergey Fedorov
2016-05-25 19:59 ` Pranith Kumar
2016-05-25 20:02 ` Sergey Fedorov
2016-05-25 19:50 ` Richard Henderson
2016-05-25 19:57 ` Pranith Kumar
2016-05-25 19:56 ` Pranith Kumar
2016-05-26 16:09 ` Alex Bennée
2016-05-24 17:18 ` [RFC PATCH 3/3] tcg: Add frontend support for fence gen in ARMv7 Pranith Kumar
2016-05-24 17:18 ` [Qemu-devel] " Pranith Kumar
2016-05-25 17:36 ` Richard Henderson
2016-05-25 17:36 ` [Qemu-devel] " Richard Henderson
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