From: Peter Xu <peterx@redhat.com>
To: Igor Mammedov <imammedo@redhat.com>
Cc: qemu-devel@nongnu.org, ehabkost@redhat.com, mst@redhat.com,
jasowang@redhat.com, rkrcmar@redhat.com,
alex.williamson@redhat.com, jan.kiszka@web.de, wexu@redhat.com,
pbonzini@redhat.com, marcel@redhat.com, davidkiarie4@gmail.com,
rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v8 04/25] acpi: add DMAR scope definition for root IOAPIC
Date: Thu, 2 Jun 2016 12:16:20 +0800 [thread overview]
Message-ID: <20160602041620.GA3477@pxdev.xzpeter.org> (raw)
In-Reply-To: <20160601145638.45ab838a@nial.brq.redhat.com>
On Wed, Jun 01, 2016 at 02:56:38PM +0200, Igor Mammedov wrote:
[...]
> > @@ -2561,6 +2563,9 @@ build_dmar_q35(MachineState *ms, GArray *table_data, GArray *linker)
> > AcpiTableDmar *dmar;
> > AcpiDmarHardwareUnit *drhd;
> > uint8_t dmar_flags = 0;
> > + AcpiDmarDeviceScope *scope = NULL;
> > + /* Root complex IOAPIC use one path[0] only */
> > + uint16_t scope_size = sizeof(*scope) + sizeof(uint16_t);
> ioapic_scope_size
> sizeof(scope->path[0]) /* space for IOxAPIC path */
Agree on both.
>
> > if (ms->iommu_intr) {
> > /* enable INTR for the IOMMU device */
> > @@ -2574,11 +2579,19 @@ build_dmar_q35(MachineState *ms, GArray *table_data, GArray *linker)
> > /* DMAR Remapping Hardware Unit Definition structure */
> > drhd = acpi_data_push(table_data, sizeof(*drhd));
> sizeof(*drhd) + ioapic_scope_size
>
> > drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
> > - drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
> > + drhd->length = cpu_to_le16(sizeof(*drhd) + scope_size);
> > drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
> > drhd->pci_segment = cpu_to_le16(0);
> > drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
> >
> > + /* Scope definition for the root-complex IOAPIC */
> > + scope = acpi_data_push(table_data, scope_size);
> no need for this as previous push took care about all space we need for scope
> ioapic_scope = &drhd->scope[0];
Both work for me. I can do a switch.
>
> > + scope->entry_type = cpu_to_le16(ACPI_DMAR_DEV_SCOPE_TYPE_IOAPIC);
> entry_type is 1 byte long, doing cpu_to_le16 on bigendian host
> will always result in 0 being written there
>
> > + scope->length = scope_size;
> > + scope->enumeration_id = cpu_to_le16(ACPI_BUILD_IOAPIC_ID);
> > + scope->bus = cpu_to_le16(Q35_PSEUDO_BUS_PLATFORM);
> ditto for above 2 fields
Ah, didn't notice these lines after it worked. For the three places, I
should remove cpu_to_le16().
[...]
> > +/*
> > + * Arbitary but unique BNF number for IOAPIC device. This is only
> > + * used when interrupt remapping is enabled.
> you encode it in DMAR unconditionally so not "only"
Okay. Removing the 2nd sentence.
Thanks for the review comments, Igor!
-- peterx
next prev parent reply other threads:[~2016-06-02 4:16 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-30 10:31 [Qemu-devel] [PATCH v8 00/25] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 01/25] acpi: enable INTR for DMAR report structure Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 02/25] intel_iommu: allow queued invalidation for IR Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 03/25] intel_iommu: set IR bit for ECAP register Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 04/25] acpi: add DMAR scope definition for root IOAPIC Peter Xu
2016-06-01 12:56 ` Igor Mammedov
2016-06-02 4:16 ` Peter Xu [this message]
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 05/25] intel_iommu: define interrupt remap table addr register Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 06/25] intel_iommu: handle interrupt remap enable Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 07/25] intel_iommu: define several structs for IOMMU IR Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 08/25] x86-iommu: introduce parent class Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 09/25] x86-iommu: provide x86_iommu_get_default Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 10/25] x86-iommu: q35: generalize find_add_as() Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 11/25] intel_iommu: add IR translation faults defines Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 12/25] intel_iommu: Add support for PCI MSI remap Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 13/25] q35: ioapic: add support for emulated IOAPIC IR Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 14/25] ioapic: introduce ioapic_entry_parse() helper Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 15/25] intel_iommu: add support for split irqchip Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 16/25] q35: add "intremap" parameter to enable IR Peter Xu
2016-05-30 12:43 ` Jan Kiszka
2016-05-30 13:33 ` Peter Xu
2016-06-02 9:21 ` Marcel Apfelbaum
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 17/25] x86-iommu: introduce IEC notifiers Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 18/25] ioapic: register IOMMU IEC notifier for ioapic Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 19/25] intel_iommu: Add support for Extended Interrupt Mode Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 20/25] intel_iommu: add SID validation for IR Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 21/25] kvm-irqchip: simplify kvm_irqchip_add_msi_route Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 22/25] kvm-irqchip: i386: add hook for add/remove virq Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 23/25] kvm-irqchip: x86: add msi route notify fn Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 24/25] kvm-irqchip: do explicit commit when update irq Peter Xu
2016-05-30 10:31 ` [Qemu-devel] [PATCH v8 25/25] intel_iommu: support all masks in interrupt entry cache invalidation Peter Xu
2016-05-30 10:38 ` [Qemu-devel] [PATCH v8 00/25] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160602041620.GA3477@pxdev.xzpeter.org \
--to=peterx@redhat.com \
--cc=alex.williamson@redhat.com \
--cc=davidkiarie4@gmail.com \
--cc=ehabkost@redhat.com \
--cc=imammedo@redhat.com \
--cc=jan.kiszka@web.de \
--cc=jasowang@redhat.com \
--cc=marcel@redhat.com \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=rkrcmar@redhat.com \
--cc=rth@twiddle.net \
--cc=wexu@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.