From mboxrd@z Thu Jan  1 00:00:00 1970
From: =?iso-8859-1?Q?N=E9lio?= Laranjeiro <nelio.laranjeiro@6wind.com>
Subject: Re: [PATCH 00/24] Refactor mlx5 to improve performance
Date: Tue, 14 Jun 2016 08:57:52 +0200
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To: Javier Blazquez <jblazquez@riotgames.com>
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On Mon, Jun 13, 2016 at 11:50:48AM -0700, Javier Blazquez wrote:
>[...]=20
> This is a very exciting patch. I applied it and reran some microbenchma=
rks
> of mine that test the TX and RX paths separately. These are the results=
 I
> got:
>=20
> TX path (burst =3D 64 packets)
>=20
> 1 thread - 2 ports - 4 queues per port: 39Mpps =3D> 48Mpps
> 2 threads - 2 ports - 2 queues per port: 60Mpps =3D> 60Mpps (hardware
> limitation?)

To be able to reach higher values you will need to configure the inline
feature with the device argument txq_inline, and only activate it with
more than 1 queue, this can be done with the txq_min_inline argument.

This feature helps the NIC by reducing the PCI back-pressure, in
counterpart it will consume more CPU cycles.

You can take a look to the NIC documentation (doc/guides/nics/mlx5.rst)
updated in this path-set which explains both txq_inline and
txqs_min_inline device arguments.

> RX path (burst =3D 32 packets)
>=20
> 1 thread - 2 ports - 4 queues per port: 38Mpps =3D> 46Mpps
> 2 threads - 2 ports - 2 queues per port: 43Mpps =3D> 50Mpps
>=20
> The tests were run on the following hardware, using DPDK master with th=
is
> patch and the "Miscellaneous fixes for mlx4 and mlx5" patch applied:
>=20
> 2x Intel Xeon E5-2680 v3 2.5GHz
> 64GB DDR4-2133
> 1x Mellanox ConnectX-4 EN, 40/56GbE dual-port, PCIe3.0 x8 (MCX414A-BCAT=
)
>=20
> I haven't test it extensively outside of these microbenchmarks, but so =
far
> this patch has been working great on my end, so:
>=20
> tested-by: Javier Blazquez <jblazquez@riotgames.com>

Regards,

--=20
N=E9lio Laranjeiro
6WIND