From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35481) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bD3m4-0004o0-ID for qemu-devel@nongnu.org; Wed, 15 Jun 2016 01:54:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bD3m3-0005r8-Bk for qemu-devel@nongnu.org; Wed, 15 Jun 2016 01:54:00 -0400 Date: Wed, 15 Jun 2016 15:06:20 +1000 From: David Gibson Message-ID: <20160615050620.GD21472@voom.fritz.box> References: <1465795496-15071-1-git-send-email-clg@kaod.org> <1465795496-15071-7-git-send-email-clg@kaod.org> <20160615011906.GA4882@voom.fritz.box> <1465965116.30200.51.camel@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="LKTjZJSUETSlgu2t" Content-Disposition: inline In-Reply-To: <1465965116.30200.51.camel@kernel.crashing.org> Subject: Re: [Qemu-devel] [PATCH 06/10] ppc: Rework generation of priv and inval interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: =?iso-8859-1?Q?C=E9dric?= Le Goater , qemu-ppc@nongnu.org, qemu-devel@nongnu.org --LKTjZJSUETSlgu2t Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jun 15, 2016 at 02:31:56PM +1000, Benjamin Herrenschmidt wrote: > On Wed, 2016-06-15 at 11:19 +1000, David Gibson wrote: > >=20 > > > =A0static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) > > > @@ -4348,9 +4371,15 @@ static inline void gen_op_mfspr(DisasContext *= ctx) > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0= =A0=A0=A0=A0=A0=A0=A0TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0} > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0} > > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0gen_inval_exception(ctx, POWERPC= _EXCP_PRIV_REG); > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0gen_priv_exception(ctx, POWERPC_= EXCP_PRIV_REG); > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0} > > > =A0=A0=A0=A0=A0} else { > > > +=A0=A0=A0=A0=A0=A0=A0=A0/* ISA 2.07 defines these as no-ops */ > > > +=A0=A0=A0=A0=A0=A0=A0=A0if ((ctx->insns_flags2 & PPC2_ISA207S) && > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0(sprn >=3D 808 && sprn <=3D 811)= ) { > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0/* This is a nop */ > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0return; > > > +=A0=A0=A0=A0=A0=A0=A0=A0} > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0/* Not defined */ > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0fprintf(stderr, "Trying to read invalid sp= r %d (0x%03x) at " > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0TARGET_FMT_lx "\n"= , sprn, sprn, ctx->nip - 4); > > > @@ -4358,9 +4387,18 @@ static inline void gen_op_mfspr(DisasContext *= ctx) > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0qemu_log("Trying to read inval= id spr %d (0x%03x) at " > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0TAR= GET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); > > > =A0=A0=A0=A0=A0=A0=A0=A0=A0} > > > -=A0=A0=A0=A0=A0=A0=A0=A0/* Only generate an exception in user space,= otherwise this is a nop */ > > > -=A0=A0=A0=A0=A0=A0=A0=A0if (ctx->pr) { > > > -=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0gen_inval_exception(ctx, POWERPC= _EXCP_INVAL_SPR); > > > + > > > +=A0=A0=A0=A0=A0=A0=A0=A0/* The behaviour depends on MSR:PR and SPR# = bit 0x10, > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0* it can generate a priv, a hv emu or a n= o-op > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0*/ > > > +=A0=A0=A0=A0=A0=A0=A0=A0if (sprn & 0x10) { > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0if (ctx->pr) { > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0gen_priv_exception(c= tx, POWERPC_EXCP_INVAL_SPR); > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0} > > > +=A0=A0=A0=A0=A0=A0=A0=A0} else { > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0if (ctx->pr || sprn =3D=3D 0 || = sprn =3D=3D 4 || sprn =3D=3D 5 || sprn =3D=3D 6) { > > > +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0gen_hvpriv_exception= (ctx, POWERPC_EXCP_INVAL_SPR); > >=20 > > Just double checking this logic.=A0=A0So in this case we get an excepti= on > > to the hypervisor if executed in guest user mode, but a no-op if > >=20 > > executed in guest supervisor mode.=A0=A0That seems.. odd. >=20 > >From the architecture: >=20 > * if spr 0 =3D0: > - if MSR PR =3D1: Hypervisor Emulation Assistance > interrupt > - if MSR PR =3D0: Hypervisor Emulation Assistance > interrupt for SPRs 0, 4, 5, and 6 and no opera- > tion (i.e. the instruction is treated as a no-op) > for all other SPRs > =84 > * if spr 0 =3D1: > - if MSR PR =3D1: Privileged Instruction type Pro- > gram interrupt > - if MSR PR =3D0: no operation (i.e. the instruction > is treated as a no-op) >=20 > IE. SPRs with 0x10 are supervisor priv, so PR access will trap to > the OS, whether they are implemented or not. >=20 > Otherwise, you get the "system illegal isntruction" handler which > is turned into an HVPRIV on all recent processors (the exception code > will turn that back into a 0x700 if the processor doesn't support > HVPRIV). >=20 > It was done this way so that an OS (guest) can context switch a bunch > of supervisor SPRs without having to test if they individually exist > on a given processor. Huh. Alright then. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --LKTjZJSUETSlgu2t Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXYOJMAAoJEGw4ysog2bOSUNwQAJsArCzomb8kN/PMJOrcZqTz 0fBeJQm5FDcVItnk3rAL3Wnlg40sRGKspRlSXUheAtqSQ8t51mKXR7hnurs47dDl f7SP9Jiky0PUDVNrQazpGds3BS9tomxX4HqcWZZyG2gxD9D5/r5UDFfaijN4rLJL qHYVWYnZqmcvnWniDQL4FKhXoVFzGvXr1RQDzTxgP/UtlIdmhwY+fWXiT5IJNz5p BNf3SmzduvcjeOnXhzuynj2bsN1fd65qw6m7hKRxLbsO7dkKq2p1I/yR71qNHnG4 xI8C6+/Lp/tWFCpsDTXS6a+4u5ymjTOm0qZxlUUjIQih2yZwyOyUTZmU+IMheh5H JH2dE2z1BeFu3XpX0a3Qz/4MtlXWlhyOfwl3+yoUgqrm5cDzHAH1+Ki8ID5ZbjNL XVs3muNIJ1GAgshBgiaLxzZwMR+lNYcD7u8Nfa/WwG4/gA5IsNljOI4Ap9gbwkuR qHubQCF+HAt0z/MfR3lqkM6CQoOzqnDW4S2jSUthGpSsuPngws7vXMUOGzS1vXZo 4CIUV//oU0oEpXZ9bWnbKlDUICphFIKBp/yhzkJR18sOmBzYuMYPoHcC1cpAZBoh A209xF8/tOitTVRtLe299cwhaFNjFYV1YsWKQnETKZuByE6iC3TKti1v/M1kxpH3 K6FobOx5SfUlhyTNruc7 =yxgc -----END PGP SIGNATURE----- --LKTjZJSUETSlgu2t--