diff for duplicates of <20160622181305.GE4329@intel.com> diff --git a/a/1.txt b/N1/1.txt index 2b3de7d..391f499 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ On Fri, Jun 17, 2016 at 09:40:45PM +0300, Imre Deak wrote: > On Fri, 2016-05-13 at 20:53 +0300, ville.syrjala@linux.intel.com wrote: -> > From: Ville Syrjälä <ville.syrjala@linux.intel.com> +> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > > > During hibernation the cached DP port register value will be left with > > whatever value we have there when we create the hibernation image. @@ -15,8 +15,8 @@ On Fri, Jun 17, 2016 at 09:40:45PM +0300, Imre Deak wrote: > > intel_dp_link_down() and potentially confuse the hardware. > > > > This was caught by the following assert -> > WARNING: CPU: 3 PID: 5288 at ../drivers/gpu/drm/i915/intel_dp.c:2184 assert_edp_pll+0x99/0xa0 [i915] -> > eDP PLL state assertion failure (expected on, current off) +> > �WARNING: CPU: 3 PID: 5288 at ../drivers/gpu/drm/i915/intel_dp.c:2184 assert_edp_pll+0x99/0xa0 [i915] +> > �eDP PLL state assertion failure (expected on, current off) > > on account of the eDP PLL getting prematurely turned off when > > shutting down the port, since the DP_PLL_ENABLE bit wasn't set > > in the cached register value. @@ -50,7 +50,7 @@ going on there. > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: stable@vger.kernel.org > > Fixes: 6fec76628333 ("drm/i915: Use intel_dp->DP in eDP PLL setup") -> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> +> > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > Reviewed-by: Imre Deak <imre.deak@intel.com> @@ -58,37 +58,33 @@ Pushed to dinq. Thanks for the review. > > > --- -> > drivers/gpu/drm/i915/intel_dp.c | 8 +++++--- -> > 1 file changed, 5 insertions(+), 3 deletions(-) +> > �drivers/gpu/drm/i915/intel_dp.c | 8 +++++--- +> > �1 file changed, 5 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index 36330026ceff..a3f38115a3bd 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -4522,13 +4522,15 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) -> > -> > void intel_dp_encoder_reset(struct drm_encoder *encoder) -> > { +> > � +> > �void intel_dp_encoder_reset(struct drm_encoder *encoder) +> > �{ > > - struct intel_dp *intel_dp; > > + struct drm_i915_private *dev_priv = to_i915(encoder->dev); > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > + > > + if (!HAS_DDI(dev_priv)) > > + intel_dp->DP = I915_READ(intel_dp->output_reg); -> > -> > if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) -> > return; -> > +> > � +> > � if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) +> > � return; +> > � > > - intel_dp = enc_to_intel_dp(encoder); > > - -> > pps_lock(intel_dp); -> > -> > /* +> > � pps_lock(intel_dp); +> > � +> > � /* -- -Ville Syrjälä +Ville Syrj�l� Intel OTC -_______________________________________________ -Intel-gfx mailing list -Intel-gfx@lists.freedesktop.org -https://lists.freedesktop.org/mailman/listinfo/intel-gfx diff --git a/a/content_digest b/N1/content_digest index d7f35e5..a2f5842 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,17 @@ "ref\01463162036-27931-1-git-send-email-ville.syrjala@linux.intel.com\0" "ref\01466188845.2572.16.camel@intel.com\0" "From\0Ville Syrj\303\244l\303\244 <ville.syrjala@linux.intel.com>\0" - "Subject\0Re: [PATCH] drm/i915: Refresh cached DP port register value on resume\0" + "Subject\0Re: [Intel-gfx] [PATCH] drm/i915: Refresh cached DP port register value on resume\0" "Date\0Wed, 22 Jun 2016 21:13:05 +0300\0" "To\0Imre Deak <imre.deak@intel.com>\0" - "Cc\0Jani Nikula <jani.nikula@intel.com>" - intel-gfx@lists.freedesktop.org + "Cc\0intel-gfx@lists.freedesktop.org" + Jani Nikula <jani.nikula@intel.com> " stable@vger.kernel.org\0" "\00:1\0" "b\0" "On Fri, Jun 17, 2016 at 09:40:45PM +0300, Imre Deak wrote:\n" "> On Fri, 2016-05-13 at 20:53 +0300, ville.syrjala@linux.intel.com wrote:\n" - "> > From: Ville Syrj\303\244l\303\244 <ville.syrjala@linux.intel.com>\n" + "> > From: Ville Syrj\303\257\302\277\302\275l\303\257\302\277\302\275 <ville.syrjala@linux.intel.com>\n" "> > \n" "> > During hibernation the cached DP port register value will be left with\n" "> > whatever value we have there when we create the hibernation image.\n" @@ -26,8 +26,8 @@ "> > intel_dp_link_down() and potentially confuse the hardware.\n" "> > \n" "> > This was caught by the following assert\n" - "> > \302\240WARNING: CPU: 3 PID: 5288 at ../drivers/gpu/drm/i915/intel_dp.c:2184 assert_edp_pll+0x99/0xa0 [i915]\n" - "> > \302\240eDP PLL state assertion failure (expected on, current off)\n" + "> > \303\257\302\277\302\275WARNING: CPU: 3 PID: 5288 at ../drivers/gpu/drm/i915/intel_dp.c:2184 assert_edp_pll+0x99/0xa0 [i915]\n" + "> > \303\257\302\277\302\275eDP PLL state assertion failure (expected on, current off)\n" "> > on account of the eDP PLL getting prematurely turned off when\n" "> > shutting down the port, since the DP_PLL_ENABLE bit wasn't set\n" "> > in the cached register value.\n" @@ -61,7 +61,7 @@ "> > Cc: Jani Nikula <jani.nikula@intel.com>\n" "> > Cc: stable@vger.kernel.org\n" "> > Fixes: 6fec76628333 (\"drm/i915: Use intel_dp->DP in eDP PLL setup\")\n" - "> > Signed-off-by: Ville Syrj\303\244l\303\244 <ville.syrjala@linux.intel.com>\n" + "> > Signed-off-by: Ville Syrj\303\257\302\277\302\275l\303\257\302\277\302\275 <ville.syrjala@linux.intel.com>\n" "> \n" "> Reviewed-by: Imre Deak <imre.deak@intel.com>\n" "\n" @@ -69,39 +69,35 @@ "\n" "> \n" "> > ---\n" - "> > \302\240drivers/gpu/drm/i915/intel_dp.c | 8 +++++---\n" - "> > \302\2401 file changed, 5 insertions(+), 3 deletions(-)\n" + "> > \303\257\302\277\302\275drivers/gpu/drm/i915/intel_dp.c | 8 +++++---\n" + "> > \303\257\302\277\302\2751 file changed, 5 insertions(+), 3 deletions(-)\n" "> > \n" "> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c\n" "> > index 36330026ceff..a3f38115a3bd 100644\n" "> > --- a/drivers/gpu/drm/i915/intel_dp.c\n" "> > +++ b/drivers/gpu/drm/i915/intel_dp.c\n" "> > @@ -4522,13 +4522,15 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)\n" - "> > \302\240\n" - "> > \302\240void intel_dp_encoder_reset(struct drm_encoder *encoder)\n" - "> > \302\240{\n" + "> > \303\257\302\277\302\275\n" + "> > \303\257\302\277\302\275void intel_dp_encoder_reset(struct drm_encoder *encoder)\n" + "> > \303\257\302\277\302\275{\n" "> > -\tstruct intel_dp *intel_dp;\n" "> > +\tstruct drm_i915_private *dev_priv = to_i915(encoder->dev);\n" "> > +\tstruct intel_dp *intel_dp = enc_to_intel_dp(encoder);\n" "> > +\n" "> > +\tif (!HAS_DDI(dev_priv))\n" "> > +\t\tintel_dp->DP = I915_READ(intel_dp->output_reg);\n" - "> > \302\240\n" - "> > \302\240\tif (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)\n" - "> > \302\240\t\treturn;\n" - "> > \302\240\n" + "> > \303\257\302\277\302\275\n" + "> > \303\257\302\277\302\275\tif (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)\n" + "> > \303\257\302\277\302\275\t\treturn;\n" + "> > \303\257\302\277\302\275\n" "> > -\tintel_dp = enc_to_intel_dp(encoder);\n" "> > -\n" - "> > \302\240\tpps_lock(intel_dp);\n" - "> > \302\240\n" - "> > \302\240\t/*\n" + "> > \303\257\302\277\302\275\tpps_lock(intel_dp);\n" + "> > \303\257\302\277\302\275\n" + "> > \303\257\302\277\302\275\t/*\n" "\n" "-- \n" - "Ville Syrj\303\244l\303\244\n" - "Intel OTC\n" - "_______________________________________________\n" - "Intel-gfx mailing list\n" - "Intel-gfx@lists.freedesktop.org\n" - https://lists.freedesktop.org/mailman/listinfo/intel-gfx + "Ville Syrj\303\257\302\277\302\275l\303\257\302\277\302\275\n" + Intel OTC -2330a9bb2c9cc3e8fbefd9e6f64940944e9b85189f765192fa4ceed779e07541 +9418306cadbcfd1421aba5078595b82f1de0c1a60edc8e6dbe002acca46a74e4
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.