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From: "Luck, Tony" <tony.luck@intel.com>
To: Borislav Petkov <bp@suse.de>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
	Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@elte.hu>,
	"H. Peter Anvin" <h.peter.anvin@intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Stephane Eranian <eranian@google.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH] cacheinfo: Introduce cache id
Date: Fri, 1 Jul 2016 09:50:41 -0700	[thread overview]
Message-ID: <20160701165041.GA18186@intel.com> (raw)
In-Reply-To: <20160701102143.GB4749@pd.tnic>

On Fri, Jul 01, 2016 at 12:21:43PM +0200, Borislav Petkov wrote:
> On Wed, Jun 29, 2016 at 06:56:10PM -0700, Fenghua Yu wrote:
> > From: Fenghua Yu <fenghua.yu@intel.com>
> > 
> > Each cache node is described by cacheinfo and is a unique node across
> 
> What is a cache node?

Clearly not a good name for the concept we are trying to communicate here.
Better suggestions welcome!

Here's the situation.  We have lots of (mostly) independent caches on a system.
The L3 cache (also called LLC - Last Level Cache - in some documentation) is
usually shared by all cpus on a physical socket. The L1 and L2 caches are
typically local to a core, so only shared by the hyperthreads on a core.
But I say "usually" and "typically" because the architecture doesn't require
that. We could have multiple separate L3 caches on a socket with a subset of
cpus assigned to each of them. We could have an L2 cache that is shared by
two or more cores.

/sys/devices/system/cpu/cpu*/cache/index*/shared_cpu_{list,map} allow for
arbitrary sharing schemes and tell you which caches are shared among which
groups of Linux logical cpus.

What we don't have is a *name* for each cache.

CAT (Intel Cache Allocation Technology) allows us to partition caches
on a per task basis. E.g. process A can only use 20% of the L3 cache on
socket0, process B can use 40% (that doesn't overlap with the 20% assigned
to process A - or perhaps does overlap - the feature is quite versatile).
But since caches aren't necessarily mapped to sockets or cores, we need a
name for each cache.


> And since this patch adds the generic functionality and then enables it
> on x86, it should be split into two patches.

Mea culpa.  Fenghua had split this as you suggest, and I said "with just
23 lines added this can be one patch". Sorry Fenghua.

-Tony

  reply	other threads:[~2016-07-01 16:50 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-30  1:56 [PATCH] cacheinfo: Introduce cache id Fenghua Yu
2016-06-30  1:56 ` Fenghua Yu
2016-07-01 10:21 ` Borislav Petkov
2016-07-01 16:50   ` Luck, Tony [this message]
2016-07-01 17:27     ` Borislav Petkov
2016-07-01 18:00       ` Luck, Tony
2016-07-01 18:29         ` Borislav Petkov
2016-07-01 18:32           ` Yu, Fenghua
2016-07-01 18:40             ` Borislav Petkov
2016-07-01 19:08               ` Yu, Fenghua
2016-07-04 17:29                 ` Borislav Petkov
2016-07-01 18:01       ` Yu, Fenghua
2016-07-01 18:35         ` Borislav Petkov
2016-07-01 19:24           ` Yu, Fenghua
2016-07-04 17:58             ` Borislav Petkov

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