diff for duplicates of <20160707160023.GF1835@localhost.localdomain> diff --git a/a/1.txt b/N1/1.txt index e455e32..45f7831 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -33,8 +33,8 @@ Apologies for being unclear there, I was really just referring to where the source for each clock is coming from. Given controllers C1 and C2, and putting the clock in brackets afterwards: -C1(MCLK@26MHz) is the parent of C2(FLL@24.576MHz) which is the parent -of C1(AUDIO@24.576MHz). Which makes C2 both a parent and child of +C1(MCLK at 26MHz) is the parent of C2(FLL at 24.576MHz) which is the parent +of C1(AUDIO at 24.576MHz). Which makes C2 both a parent and child of C1. Its probably not that likely but I could see it happening. > > I had also been leaning more towards a lock per clock rather diff --git a/a/content_digest b/N1/content_digest index 7766591..609fe41 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -6,21 +6,10 @@ "ref\0913d98f6-0d7c-63e3-8748-961eafd776f4@osg.samsung.com\0" "ref\020160707120626.GE1835@localhost.localdomain\0" "ref\0577E4E29.5080103@samsung.com\0" - "From\0Charles Keepax <ckeepax@opensource.wolfsonmicro.com>\0" - "Subject\0Re: clk: Per controller locks (prepare & enable)\0" + "From\0ckeepax@opensource.wolfsonmicro.com (Charles Keepax)\0" + "Subject\0clk: Per controller locks (prepare & enable)\0" "Date\0Thu, 7 Jul 2016 17:00:23 +0100\0" - "To\0Krzysztof Kozlowski <k.kozlowski@samsung.com>\0" - "Cc\0Javier Martinez Canillas <javier@osg.samsung.com>" - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - <linux-clk@vger.kernel.org> - <linux-kernel@vger.kernel.org> - linux-arm-kernel <linux-arm-kernel@lists.infradead.org> - Tomasz Figa <tomasz.figa@gmail.com> - Sylwester Nawrocki <s.nawrocki@samsung.com> - Andrzej Hajda <a.hajda@samsung.com> - Marek Szyprowski <m.szyprowski@samsung.com> - " Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Thu, Jul 07, 2016 at 02:42:17PM +0200, Krzysztof Kozlowski wrote:\n" @@ -58,8 +47,8 @@ "where the source for each clock is coming from. Given controllers\n" "C1 and C2, and putting the clock in brackets afterwards:\n" "\n" - "C1(MCLK@26MHz) is the parent of C2(FLL@24.576MHz) which is the parent\n" - "of C1(AUDIO@24.576MHz). Which makes C2 both a parent and child of\n" + "C1(MCLK at 26MHz) is the parent of C2(FLL at 24.576MHz) which is the parent\n" + "of C1(AUDIO at 24.576MHz). Which makes C2 both a parent and child of\n" "C1. Its probably not that likely but I could see it happening.\n" "\n" "> > I had also been leaning more towards a lock per clock rather\n" @@ -118,4 +107,4 @@ "Thanks,\n" Charles -75cc35df8d5cddc4da6738f46fc4aca7f0c5fa31f5bd23a0bb5a9471adc2d59d +6acef3ef5e895c517922c8cd733f7c15496d7b0f1bf4e938b063135e2bd2ef5a
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