From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47941) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNn7y-00009s-9Y for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bNn7x-0001c0-4y for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:58 -0400 Received: from mail-yw0-x244.google.com ([2607:f8b0:4002:c05::244]:36559) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNn7x-0001bv-0H for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:57 -0400 Received: by mail-yw0-x244.google.com with SMTP id y188so5582804ywf.3 for ; Thu, 14 Jul 2016 13:20:56 -0700 (PDT) From: Pranith Kumar Date: Thu, 14 Jul 2016 16:20:21 -0400 Message-Id: <20160714202026.9727-10-bobby.prani@gmail.com> In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com> References: <20160714202026.9727-1-bobby.prani@gmail.com> Subject: [Qemu-devel] [PATCH v4 09/14] tcg/sparc: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , "open list:All patches CC here" Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, pbonzini@redhat.com, peter.maydell@linaro.org, Blue Swirl Cc: Blue Swirl Signed-off-by: Pranith Kumar Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.inc.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 8e98172..04a6404 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -249,6 +249,8 @@ static const int tcg_target_call_oarg_regs[] = { #define STWA (INSN_OP(3) | INSN_OP3(0x14)) #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) +#define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13)) + #ifndef ASI_PRIMARY_LITTLE #define ASI_PRIMARY_LITTLE 0x88 #endif @@ -835,6 +837,24 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest) tcg_out_nop(s); } +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + uint8_t bar_opcode = MEMBAR; + if (a0 & TCG_MO_LD_LD) { + /* #LoadLoad */ + bar_opcode |= 0x5; + } + if (a0 & TCG_MO_ST_ST) { + /* #StoreStore */ + bar_opcode |= 0xa; + } + if (a0 & (TCG_MO_LD_ST | TCG_MO_ST_LD)) { + /* #StoreLoad | #LoadStore */ + bar_opcode |= 0xf; + } + tcg_out32(s, bar_opcode); +} + #ifdef CONFIG_SOFTMMU static tcg_insn_unit *qemu_ld_trampoline[16]; static tcg_insn_unit *qemu_st_trampoline[16]; @@ -1460,6 +1480,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); break; + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -1561,6 +1585,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_qemu_st_i32, { "sZ", "A" } }, { INDEX_op_qemu_st_i64, { "SZ", "A" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.9.0