From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47815) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNn7o-0008Rq-VK for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bNn7m-0001ZK-Ve for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:48 -0400 Received: from mail-yw0-x241.google.com ([2607:f8b0:4002:c05::241]:36554) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNn7m-0001Z7-S4 for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:46 -0400 Received: by mail-yw0-x241.google.com with SMTP id y188so5582580ywf.3 for ; Thu, 14 Jul 2016 13:20:46 -0700 (PDT) From: Pranith Kumar Date: Thu, 14 Jul 2016 16:20:14 -0400 Message-Id: <20160714202026.9727-3-bobby.prani@gmail.com> In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com> References: <20160714202026.9727-1-bobby.prani@gmail.com> Subject: [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , "open list:i386 target" Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, pbonzini@redhat.com, peter.maydell@linaro.org Generate a 'lock orl $0,0(%esp)' instruction for ordering instead of mfence which has similar ordering semantics. Signed-off-by: Pranith Kumar --- tcg/i386/tcg-target.inc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 6f8cdca..a516ec9 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -686,6 +686,18 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) } } +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + /* lock orl $0,0(%esp) is used instead of mfence, + * sfence/lfence are not generated + */ + if (a0 & TCG_MO_ST_LD) { + tcg_out8(s, 0xf0); + tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0); + tcg_out8(s, 0); + } +} + static inline void tcg_out_push(TCGContext *s, int reg) { tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0); @@ -2130,6 +2142,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_mb: + tcg_debug_assert(args[0] != 0); + tcg_out_mb(s, args[0]); + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -2195,6 +2211,8 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } }, { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } }, + { INDEX_op_mb, { } }, + #if TCG_TARGET_REG_BITS == 32 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } }, { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } }, -- 2.9.0