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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id v68sm1634604ywg.31.2016.07.14.13.20.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jul 2016 13:20:47 -0700 (PDT) From: Pranith Kumar To: Claudio Fontana , Richard Henderson , qemu-arm@nongnu.org (open list:AArch64 target), qemu-devel@nongnu.org (open list:All patches CC here) Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org, serge.fdrv@gmail.com, pbonzini@redhat.com, peter.maydell@linaro.org, Claudio Fontana Subject: [PATCH v4 03/14] tcg/aarch64: Add support for fence Date: Thu, 14 Jul 2016 16:20:15 -0400 Message-Id: <20160714202026.9727-4-bobby.prani@gmail.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com> References: <20160714202026.9727-1-bobby.prani@gmail.com> X-TUID: e5FpmeHUZXnr Cc: Claudio Fontana Signed-off-by: Pranith Kumar --- tcg/aarch64/tcg-target.inc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 08b2d03..1d220b7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -372,6 +372,11 @@ typedef enum { I3510_EOR = 0x4a000000, I3510_EON = 0x4a200000, I3510_ANDS = 0x6a000000, + + /* System instructions. */ + DMB_ISH = 0xd50338bf, + DMB_LD = 0x00000100, + DMB_ST = 0x00000200, } AArch64Insn; static inline uint32_t tcg_in32(TCGContext *s) @@ -981,6 +986,22 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl, tcg_out_mov(s, ext, orig_rl, rl); } +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + uint32_t dmb_type = DMB_ISH; + if (a0 & (TCG_MO_LD_ST | TCG_MO_ST_LD)) { + tcg_out32(s, dmb_type | DMB_LD | DMB_ST); + return; + } + if (a0 & TCG_MO_LD_LD) { + dmb_type |= DMB_LD; + } + if (a0 & TCG_MO_ST_ST) { + dmb_type |= DMB_ST; + } + tcg_out32(s, dmb_type); +} + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) @@ -1648,6 +1669,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); break; + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -1772,6 +1797,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_muluh_i64, { "r", "r", "r" } }, { INDEX_op_mulsh_i64, { "r", "r", "r" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.9.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47878) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNn7v-00006X-9Z for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bNn7t-0001an-76 for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:54 -0400 From: Pranith Kumar Date: Thu, 14 Jul 2016 16:20:15 -0400 Message-Id: <20160714202026.9727-4-bobby.prani@gmail.com> In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com> References: <20160714202026.9727-1-bobby.prani@gmail.com> Subject: [Qemu-devel] [PATCH v4 03/14] tcg/aarch64: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Claudio Fontana , Richard Henderson , "open list:AArch64 target" , "open list:All patches CC here" Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, pbonzini@redhat.com, peter.maydell@linaro.org, Claudio Fontana Cc: Claudio Fontana Signed-off-by: Pranith Kumar --- tcg/aarch64/tcg-target.inc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 08b2d03..1d220b7 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -372,6 +372,11 @@ typedef enum { I3510_EOR = 0x4a000000, I3510_EON = 0x4a200000, I3510_ANDS = 0x6a000000, + + /* System instructions. */ + DMB_ISH = 0xd50338bf, + DMB_LD = 0x00000100, + DMB_ST = 0x00000200, } AArch64Insn; static inline uint32_t tcg_in32(TCGContext *s) @@ -981,6 +986,22 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl, tcg_out_mov(s, ext, orig_rl, rl); } +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + uint32_t dmb_type = DMB_ISH; + if (a0 & (TCG_MO_LD_ST | TCG_MO_ST_LD)) { + tcg_out32(s, dmb_type | DMB_LD | DMB_ST); + return; + } + if (a0 & TCG_MO_LD_LD) { + dmb_type |= DMB_LD; + } + if (a0 & TCG_MO_ST_ST) { + dmb_type |= DMB_ST; + } + tcg_out32(s, dmb_type); +} + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * TCGMemOpIdx oi, uintptr_t ra) @@ -1648,6 +1669,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); break; + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -1772,6 +1797,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_muluh_i64, { "r", "r", "r" } }, { INDEX_op_mulsh_i64, { "r", "r", "r" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.9.0