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[108.232.152.155]) by smtp.gmail.com with ESMTPSA id v68sm1634604ywg.31.2016.07.14.13.20.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jul 2016 13:20:51 -0700 (PDT) From: Pranith Kumar To: Andrzej Zaborowski , Richard Henderson , qemu-arm@nongnu.org (open list:ARM target), qemu-devel@nongnu.org (open list:All patches CC here) Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org, serge.fdrv@gmail.com, pbonzini@redhat.com, peter.maydell@linaro.org Subject: [PATCH v4 04/14] tcg/arm: Add support for fence Date: Thu, 14 Jul 2016 16:20:16 -0400 Message-Id: <20160714202026.9727-5-bobby.prani@gmail.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com> References: <20160714202026.9727-1-bobby.prani@gmail.com> X-TUID: 1rtGb02wxSWF Cc: Andrzej Zaborowski Cc: Peter Maydell Signed-off-by: Pranith Kumar Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 172feba..4e66bcd 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -313,6 +313,10 @@ typedef enum { INSN_LDRD_REG = 0x000000d0, INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, + + INSN_DMB_ISH = 0x5bf07ff5, + INSN_DMB_MCR = 0xba0f07ee, + } ARMInsn; #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) @@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) } } +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + if (use_armv7_instructions) { + tcg_out32(s, INSN_DMB_ISH); + } else if (use_armv6_instructions) { + tcg_out32(s, INSN_DMB_MCR); + } +} + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1923,6 +1936,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); break; + case INDEX_op_mb: + tcg_out_mb(s, args[0]); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ @@ -1997,6 +2014,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.9.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bNn7y-0000AF-Ms for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bNn7x-0001cC-Km for qemu-devel@nongnu.org; Thu, 14 Jul 2016 16:20:58 -0400 From: Pranith Kumar Date: Thu, 14 Jul 2016 16:20:16 -0400 Message-Id: <20160714202026.9727-5-bobby.prani@gmail.com> In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com> References: <20160714202026.9727-1-bobby.prani@gmail.com> Subject: [Qemu-devel] [PATCH v4 04/14] tcg/arm: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andrzej Zaborowski , Richard Henderson , "open list:ARM target" , "open list:All patches CC here" Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, pbonzini@redhat.com, peter.maydell@linaro.org Cc: Andrzej Zaborowski Cc: Peter Maydell Signed-off-by: Pranith Kumar Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 172feba..4e66bcd 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -313,6 +313,10 @@ typedef enum { INSN_LDRD_REG = 0x000000d0, INSN_STRD_IMM = 0x004000f0, INSN_STRD_REG = 0x000000f0, + + INSN_DMB_ISH = 0x5bf07ff5, + INSN_DMB_MCR = 0xba0f07ee, + } ARMInsn; #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00) @@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l) } } +static inline void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + if (use_armv7_instructions) { + tcg_out32(s, INSN_DMB_ISH); + } else if (use_armv6_instructions) { + tcg_out32(s, INSN_DMB_MCR); + } +} + #ifdef CONFIG_SOFTMMU /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, * int mmu_idx, uintptr_t ra) @@ -1923,6 +1936,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]); break; + case INDEX_op_mb: + tcg_out_mb(s, args[0]); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ case INDEX_op_call: /* Always emitted via tcg_out_call. */ @@ -1997,6 +2014,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_mb, { } }, { -1 }, }; -- 2.9.0