From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matt Roper Subject: Re: [PATCH 1/2] drm/i915/skl: Update plane watermarks atomically during plane updates Date: Tue, 19 Jul 2016 10:10:58 -0700 Message-ID: <20160719171058.GB21816@intel.com> References: <1468945856-23126-1-git-send-email-cpaul@redhat.com> <1468945856-23126-2-git-send-email-cpaul@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1468945856-23126-2-git-send-email-cpaul@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Lyude Cc: "open list:INTEL DRM DRIVERS (excluding Poulsbo, Moorestow...), linux-kernel@vger.kernel.org (open list)" , David Airlie , intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Daniel Vetter List-Id: dri-devel@lists.freedesktop.org T24gVHVlLCBKdWwgMTksIDIwMTYgYXQgMTI6MzA6NTVQTSAtMDQwMCwgTHl1ZGUgd3JvdGU6Cj4g VGhhbmtzIHRvIFZpbGxlIGZvciBzdWdnZXN0aW5nIHRoaXMgYXMgYSBwb3RlbnRpYWwgc29sdXRp b24gdG8gcGlwZQo+IHVuZGVycnVucyBvbiBTa3lsYWtlLgo+IAo+IE9uIFNreWxha2UgYWxsIG9m IHRoZSByZWdpc3RlcnMgZm9yIGNvbmZpZ3VyaW5nIHBsYW5lcywgaW5jbHVkaW5nIHRoZQo+IHJl Z2lzdGVycyBmb3IgY29uZmlndXJpbmcgdGhlaXIgd2F0ZXJtYXJrcywgYXJlIGRvdWJsZSBidWZm ZXJlZC4gTmV3Cj4gdmFsdWVzIHdyaXR0ZW4gdG8gdGhlbSB3b24ndCB0YWtlIGVmZmVjdCB1bnRp bCBzYWlkIHJlZ2lzdGVycyBhcmUKPiAiYXJtZWQiLCB3aGljaCBpcyBkb25lIGJ5IHdyaXRpbmcg dG8gdGhlIFBMQU5FX1NVUkYgKG9yIGluIHRoZSBjYXNlIG9mCj4gY3Vyc29yIHBsYW5lcywgdGhl IENVUkJBU0UgcmVnaXN0ZXIpIHJlZ2lzdGVyLgo+IAo+IFdpdGggdGhpcyBpbiBtaW5kLCB1cCB1 bnRpbCBub3cgd2UndmUgYmVlbiB1cGRhdGluZyB3YXRlcm1hcmtzIG9uIHNrbAo+IGxpa2UgdGhp czoKPiAKPiAgLSBDYWxjdWxhdGUgbmV3IHdhdGVybWFyayB2YWx1ZXMgaW4gc2tsX2NvbXB1dGVf d20oKQo+IAo+ICAtIFVwZGF0ZSBub24td2F0ZXJtYXJrIHNldHRpbmdzIGZvciBlYWNoIHBsYW5l IGluCj4gICAgc2t5bGFrZV91cGRhdGVfcHJpbWFyeV9wbGFuZSgpL2k5eHhfdXBkYXRlX2N1cnNv cigpCj4gCj4gIC0gQXJtIHBsYW5lIHJlZ2lzdGVycyB0byB1cGRhdGUgYXQgdGhlIHN0YXJ0IG9m IHRoZSBuZXh0IHZibGFuayBpbgo+ICAgIHNreWxha2VfdXBkYXRlX3ByaW1hcnlfcGxhbmUoKS9p OXh4X3VwZGF0ZV9jdXJzb3IoKQo+IAo+ICAtICpQb3NzaWJseSB1bmRlcnJ1biBoZXJlLCBzaW5j ZSB0aGUgcGxhbmUgbWF5IG5vdyBoYXZlIHVwZGF0ZWQgaXQncwo+ICAgIHNldHRpbmdzIHVzaW5n IHRoZSBvbGQgYW5kIGluc3VmZmljaWVudCB3YXRlcm1hcmsgdmFsdWVzKgo+IAo+ICAtIFVwZGF0 ZSB3YXRlcm1hcmsgc2V0dGluZ3MgaW4gc2tsX3dyaXRlX3dtX3ZhbHVlcygpCj4gCj4gIC0gKlBv c3NpYmx5IHVuZGVycnVuIGhlcmUgYXMgd2VsbCBpZiB3ZSd2ZSBwYXNzZWQgYSB2YmxhbmssCj4g ICAgY2F1c2luZyB0aGUgaGFyZHdhcmUgdG8gZ2V0IHN0dWNrIHJ1bm5pbmcgb24gaW50ZXJtZWRp YXRlIHdtIHZhbHVlcyoKPiAKPiAgLSBGaW5hbGx5IGFybSBwbGFuZSByZWdpc3RlcnMgc28gdGhl eSB1cGRhdGUgdG8gdGhlIGNvcnJlY3QgdmFsdWVzIGF0Cj4gICAgdGhlIHN0YXJ0IG9mIHRoZSBu ZXh0IHZibGFuayBpbiBza2xfd21fZmx1c2hfcGlwZSgpCgpJIHRoaW5rIHlvdSdyZSBvbiB0aGUg cmlnaHQgdHJhY2sgd2l0aCB0aGlzIHBhdGNoLCBidXQgSSBkb24ndCB0aGluayB0aGUKc2VxdWVu Y2Ugb2YgZXZlbnRzIGlzIHF1aXRlIHdoYXQgeW91IGRlc2NyaWJlIGluIHRoZSBjb21taXQgbWVz c2FnZQpoZXJlLiAgVGhlIGNhbGxzIHRvIHNreWxha2VfdXBkYXRlX3ByaW1hcnlfcGxhbmUoKS9p OXh4X3VwZGF0ZV9jdXJzb3IoKQphcmUgd2hpbGUgd2UncmUgdW5kZXIgdmJsYW5rIGV2YXNpb24s IHdoaWNoIGhhcHBlbnMgZHVyaW5nCgogIGZpbmlzaF9hdG9taWNfY29tbWl0KCkgLT4gZHJtX2F0 b21pY19oZWxwZXJfY29tbWl0X3BsYW5lc19vbl9jcnRjKCkKClRoZW4gZ2VuOSB3YXRlcm1hcmtz IGdldCB3cml0dGVuIGR1cmluZyBpbnRlbF9wcmVfcGxhbmVfdXBkYXRlKCkgZm9yCm5vbi1tb2Rl c2V0cyBvciBkdXJpbmcgY3J0Y19lbmFibGUgZm9yIG1vZGVzZXRzLiAgU28gSSBiZWxpZXZlIHRo ZQphY3R1YWwgc2VxdWVuY2Ugb2YgZXZlbnRzIGlzOgoKICAgICAgICBub24tbW9kZXNldCB7CiAg ICAgICAgIC0gY2FsY3VsYXRlIChkdXJpbmcgYXRvbWljIGNoZWNrIHBoYXNlKQogICAgICAgICAt IGZpbmlzaF9hdG9taWNfY29tbWl0OgogICAgICAgICAgIC0gaW50ZWxfcHJlX3BsYW5lX3VwZGF0 ZToKICAgICAgICAgICAgICAtIGludGVsX3VwZGF0ZV93YXRlcm1hcmtzKCkKICAgICAgICAgICAt IHt2YmxhbmsgaGFwcGVuczsgbmV3IHdhdGVybWFya3MgKyBvbGQgcGxhbmUgdmFsdWVzID0+IHVu ZGVycnVuIH0KICAgICAgICAgICAtIGRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9wbGFuZXNfb25f Y3J0YzoKICAgICAgICAgICAgICAtIHN0YXJ0IHZibGFuayBldmFzaW9uCiAgICAgICAgICAgICAg LSB3cml0ZSBuZXcgcGxhbmUgcmVnaXN0ZXJzCiAgICAgICAgICAgICAgLSBlbmQgdmJsYW5rIGV2 YXNpb24KICAgICAgICB9CgogICAgICAgIG9yCgogICAgICAgIG1vZGVzZXQgewogICAgICAgICAt IGNhbGN1bGF0ZSAoZHVyaW5nIGF0b21pYyBjaGVjayBwaGFzZSkKICAgICAgICAgLSBmaW5pc2hf YXRvbWljX2NvbW1pdDoKICAgICAgICAgICAtIGNydGNfZW5hYmxlOgogICAgICAgICAgICAgIC0g aW50ZWxfdXBkYXRlX3dhdGVybWFya3MoKQogICAgICAgICAgIC0ge3ZibGFuayBoYXBwZW5zOyBu ZXcgd2F0ZXJtYXJrcyArIG9sZCBwbGFuZSB2YWx1ZXMgPT4gdW5kZXJydW4gfQogICAgICAgICAg IC0gZHJtX2F0b21pY19oZWxwZXJfY29tbWl0X3BsYW5lc19vbl9jcnRjOgogICAgICAgICAgICAg IC0gc3RhcnQgdmJsYW5rIGV2YXNpb24KICAgICAgICAgICAgICAtIHdyaXRlIG5ldyBwbGFuZSBy ZWdpc3RlcnMKICAgICAgICAgICAgICAtIGVuZCB2YmxhbmsgZXZhc2lvbgogICAgICAgIH0KClNv IHlvdSdyZSByaWdodCB0aGF0IGZ1bmRhbWVudGFsbHkgdGhlIHByb2JsZW0gYXJpc2VzIGZyb20g dGhlCndhdGVybWFya3Mgbm90IGJlaW5nIHVwZGF0ZWQgdW5kZXIgdmJsYW5rIGV2YXNpb24gd2hl biB0aGUgY29ycmVzcG9uZGluZwpwbGFuZSB1cGRhdGVzIGhhcHBlbiAoc28gd2UgbWlnaHQgd2lu ZCB1cCB3aXRoIG5ldyB3YXRlcm1hcmtzIGJlZm9yZQp3ZSd2ZSBhY3R1YWxseSBzd2l0Y2hlZCBv dXIgcGxhbmUgcmVnaXN0ZXJzIGlmIGEgdmJsYW5rIHNuZWFrcyBpbiBpbiB0aGUKbWVhbnRpbWUp LiAgVGhlIHNlcXVlbmNlIGlzIGp1c3Qgc2xpZ2h0bHkgZGlmZmVyZW50IGZyb20gdGhlIHdheSB5 b3UnZApsaXN0ZWQgaXQgb3V0LgoKPiAKPiBOb3cgd2UgdXBkYXRlIHdhdGVybWFya3MgYXRvbWlj YWxseSBsaWtlIHRoaXM6Cj4gCj4gIC0gQ2FsY3VsYXRlIG5ldyB3YXRlcm1hcmsgdmFsdWVzIGlu IHNrbF9jb21wdXRlX3dtKCkKPiAKPiAgLSBVcGRhdGUgd2F0ZXJtYXJrIHZhbHVlcyBmb3IgZWFj aCBwbGFuZSBpbgo+ICAgIHNreWxha2Vfd3JpdGVfcGxhbmVfd20oKS9za3lsYWtlX3dyaXRlX2N1 cnNvcl93bSgpCj4gCj4gIC0gVXBkYXRlIGFsbCB0aGUgb3RoZXIgdmFsdWVzIGZvciB0aGUgcGxh bmUgKHBvc2l0aW9uLCBhZGRyZXNzLCBldGMuKQo+ICAgIGluIHNreWxha2VfdXBkYXRlX3ByaW1h cnlfcGxhbmUoKS9pOXh4X3VwZGF0ZV9jdXJzb3IoKQoKRG8gd2UgYWxzbyBuZWVkIGl0IGluIHNr bF91cGRhdGVfcGxhbmUoKSAoZnJvbSBpbnRlbF9zcHJpdGUuYyk/Cgo+IAo+ICAtIEFybSBwbGFu ZSByZWdpc3RlcnMgKGluY2x1ZGluZyB0aGUgd2F0ZXJtYXJrIHNldHRpbmdzKSB0byB1cGRhdGUg YXQKPiAgICB0aGUgc3RhcnQgb2YgdGhlIG5leHQgdmJsYW5rIGluCj4gICAgc2t5bGFrZV91cGRh dGVfcHJpbWFyeV9wbGFuZSgpL2k5eHhfdXBkYXRlX2N1cnNvcigpCj4gCj4gV2hpY2ggaXMgbW9y ZSBvZiBhIHN0ZXAgaW4gdGhlIHJpZ2h0IGRpcmVjdGlvbiB0byBmaXhpbmcgYWxsIG9mIHRoZQo+ IHVuZGVycnVuIGlzc3VlcyB3ZSdyZSBjdXJyZW50bHkgc2VlaW5nIHdpdGggc2tsCj4gCj4gU2ln bmVkLW9mZi1ieTogTHl1ZGUgUGF1bCA8Y3BhdWxAcmVkaGF0LmNvbT4KPiBDYzogc3RhYmxlQHZn ZXIua2VybmVsLm9yZwo+IENjOiBWaWxsZSBTeXJqw6Rsw6QgPHZpbGxlLnN5cmphbGFAbGludXgu aW50ZWwuY29tPgo+IENjOiBEYW5pZWwgVmV0dGVyIDxkYW5pZWwudmV0dGVyQGludGVsLmNvbT4K PiBDYzogUmFkaGFrcmlzaG5hIFNyaXBhZGEgPHJhZGhha3Jpc2huYS5zcmlwYWRhQGludGVsLmNv bT4KPiBDYzogSGFucyBkZSBHb2VkZSA8aGRlZ29lZGVAcmVkaGF0LmNvbT4gPGNwYXVsQHJlZGhh dC5jb20+Cj4gQ2M6IE1hdHQgUm9wZXIgPG1hdHRoZXcuZC5yb3BlckBpbnRlbC5jb20+Cj4gLS0t Cj4gIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYyB8IDQ3ICsrKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKwo+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9w bS5jICAgICAgfCAxNSArLS0tLS0tLS0tLS0KPiAgMiBmaWxlcyBjaGFuZ2VkLCA0OCBpbnNlcnRp b25zKCspLCAxNCBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJt L2k5MTUvaW50ZWxfZGlzcGxheS5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxh eS5jCj4gaW5kZXggZmI3ZDhmYzUuLjNkMmMxMjUgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUv ZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50 ZWxfZGlzcGxheS5jCj4gQEAgLTI5NzEsNiArMjk3MSwyNyBAQCB1MzIgc2tsX3BsYW5lX2N0bF9y b3RhdGlvbih1bnNpZ25lZCBpbnQgcm90YXRpb24pCj4gIAlyZXR1cm4gMDsKPiAgfQo+ICAKPiAr c3RhdGljIHZvaWQgc2t5bGFrZV93cml0ZV9wbGFuZV93bShzdHJ1Y3QgaW50ZWxfY3J0YyAqaW50 ZWxfY3J0YywKPiArCQkJCSAgIGludCBwbGFuZSkKPiArewo+ICsJc3RydWN0IGRybV9jcnRjICpj cnRjID0gJmludGVsX2NydGMtPmJhc2U7Cj4gKwlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0gY3J0 Yy0+ZGV2Owo+ICsJc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0gdG9faTkxNShk ZXYpOwo+ICsJc3RydWN0IHNrbF93bV92YWx1ZXMgKndtID0gJmRldl9wcml2LT53bS5za2xfcmVz dWx0czsKPiArCWludCBsZXZlbCwgbWF4X2xldmVsID0gaWxrX3dtX21heF9sZXZlbChkZXYpOwo+ ICsJZW51bSBwaXBlIHBpcGUgPSBpbnRlbF9jcnRjLT5waXBlOwo+ICsKPiArCW11dGV4X2xvY2so JmRldl9wcml2LT53bS53bV9tdXRleCk7CgpJIGRvbid0IHRoaW5rIHRoaXMgbXV0ZXggaXMgYWN0 dWFsbHkgcHJvdGVjdGluZyBhbnl0aGluZyBpbXBvcnRhbnQgaGVyZQppcyBpdD8gIFdlIGFscmVh ZHkgaGF2ZSB0aGUgY3J0YyAmIHBsYW5lIG11dGV4ZXMgYW5kIHdlJ3JlIG5vdCByZWFsbHkKdXNp bmcvdG91Y2hpbmcgYW55IGdsb2JhbCBzdGF0ZS4gIEFjdHVhbGx5LCB3ZSdyZSBjYWxsaW5nIHRo aXMgd2hpbGUKdW5kZXIgdmJsYW5rIGV2YXNpb24sIHNvIHdlJ3JlIG5vdCBhbGxvd2VkIHRvIHNs ZWVwIGhlcmUgYW55d2F5LgoKKHNhbWUgY29tbWVudCBmb3IgdGhlIGN1cnNvciB2ZXJzaW9uKQoK Ck1hdHQKCj4gKwo+ICsJZm9yIChsZXZlbCA9IDA7IGxldmVsIDwgbWF4X2xldmVsOyBsZXZlbCsr KSB7Cj4gKwkJSTkxNV9XUklURShQTEFORV9XTShwaXBlLCBwbGFuZSwgbGV2ZWwpLAo+ICsJCQkg ICB3bS0+cGxhbmVbcGlwZV1bcGxhbmVdW2xldmVsXSk7Cj4gKwl9Cj4gKwlJOTE1X1dSSVRFKFBM QU5FX1dNX1RSQU5TKHBpcGUsIHBsYW5lKSwgd20tPnBsYW5lX3RyYW5zW3BpcGVdW3BsYW5lXSk7 Cj4gKwo+ICsJbXV0ZXhfdW5sb2NrKCZkZXZfcHJpdi0+d20ud21fbXV0ZXgpOwo+ICt9Cj4gKwo+ ICBzdGF0aWMgdm9pZCBza3lsYWtlX3VwZGF0ZV9wcmltYXJ5X3BsYW5lKHN0cnVjdCBkcm1fcGxh bmUgKnBsYW5lLAo+ICAJCQkJCSBjb25zdCBzdHJ1Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqY3J0Y19z dGF0ZSwKPiAgCQkJCQkgY29uc3Qgc3RydWN0IGludGVsX3BsYW5lX3N0YXRlICpwbGFuZV9zdGF0 ZSkKPiBAQCAtMzAzMSw2ICszMDUyLDggQEAgc3RhdGljIHZvaWQgc2t5bGFrZV91cGRhdGVfcHJp bWFyeV9wbGFuZShzdHJ1Y3QgZHJtX3BsYW5lICpwbGFuZSwKPiAgCWludGVsX2NydGMtPmFkanVz dGVkX3ggPSB4X29mZnNldDsKPiAgCWludGVsX2NydGMtPmFkanVzdGVkX3kgPSB5X29mZnNldDsK PiAgCj4gKwlza3lsYWtlX3dyaXRlX3BsYW5lX3dtKGludGVsX2NydGMsIDApOwo+ICsKPiAgCUk5 MTVfV1JJVEUoUExBTkVfQ1RMKHBpcGUsIDApLCBwbGFuZV9jdGwpOwo+ICAJSTkxNV9XUklURShQ TEFORV9PRkZTRVQocGlwZSwgMCksIHBsYW5lX29mZnNldCk7Cj4gIAlJOTE1X1dSSVRFKFBMQU5F X1NJWkUocGlwZSwgMCksIHBsYW5lX3NpemUpOwo+IEBAIC0xMDIzMyw2ICsxMDI1NiwyNyBAQCBz dGF0aWMgdm9pZCBpODQ1X3VwZGF0ZV9jdXJzb3Ioc3RydWN0IGRybV9jcnRjICpjcnRjLCB1MzIg YmFzZSwKPiAgCX0KPiAgfQo+ICAKPiArc3RhdGljIHZvaWQgc2tsX3dyaXRlX2N1cnNvcl93bShz dHJ1Y3QgaW50ZWxfY3J0YyAqaW50ZWxfY3J0YykKPiArewo+ICsJc3RydWN0IGRybV9jcnRjICpj cnRjID0gJmludGVsX2NydGMtPmJhc2U7Cj4gKwlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0gY3J0 Yy0+ZGV2Owo+ICsJc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0gdG9faTkxNShk ZXYpOwo+ICsJc3RydWN0IHNrbF93bV92YWx1ZXMgKndtID0gJmRldl9wcml2LT53bS5za2xfcmVz dWx0czsKPiArCWludCBsZXZlbCwgbWF4X2xldmVsID0gaWxrX3dtX21heF9sZXZlbChkZXYpOwo+ ICsJZW51bSBwaXBlIHBpcGUgPSBpbnRlbF9jcnRjLT5waXBlOwo+ICsKPiArCW11dGV4X2xvY2so JmRldl9wcml2LT53bS53bV9tdXRleCk7Cj4gKwo+ICsJZm9yIChsZXZlbCA9IDA7IGxldmVsIDw9 IG1heF9sZXZlbDsgbGV2ZWwrKykgewo+ICsJCUk5MTVfV1JJVEUoQ1VSX1dNKHBpcGUsIGxldmVs KSwKPiArCQkJICAgd20tPnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNPUl1bbGV2ZWxdKTsKPiArCX0K PiArCUk5MTVfV1JJVEUoQ1VSX1dNX1RSQU5TKHBpcGUpLAo+ICsJCSAgIHdtLT5wbGFuZV90cmFu c1twaXBlXVtQTEFORV9DVVJTT1JdKTsKPiArCj4gKwltdXRleF91bmxvY2soJmRldl9wcml2LT53 bS53bV9tdXRleCk7Cj4gK30KPiArCj4gIHN0YXRpYyB2b2lkIGk5eHhfdXBkYXRlX2N1cnNvcihz dHJ1Y3QgZHJtX2NydGMgKmNydGMsIHUzMiBiYXNlLAo+ICAJCQkgICAgICAgY29uc3Qgc3RydWN0 IGludGVsX3BsYW5lX3N0YXRlICpwbGFuZV9zdGF0ZSkKPiAgewo+IEBAIC0xMDI0Miw2ICsxMDI4 Niw5IEBAIHN0YXRpYyB2b2lkIGk5eHhfdXBkYXRlX2N1cnNvcihzdHJ1Y3QgZHJtX2NydGMgKmNy dGMsIHUzMiBiYXNlLAo+ICAJaW50IHBpcGUgPSBpbnRlbF9jcnRjLT5waXBlOwo+ICAJdWludDMy X3QgY250bCA9IDA7Cj4gIAo+ICsJaWYgKElTX1NLWUxBS0UoZGV2X3ByaXYpKQo+ICsJCXNrbF93 cml0ZV9jdXJzb3Jfd20oaW50ZWxfY3J0Yyk7Cj4gKwo+ICAJaWYgKHBsYW5lX3N0YXRlICYmIHBs YW5lX3N0YXRlLT52aXNpYmxlKSB7Cj4gIAkJY250bCA9IE1DVVJTT1JfR0FNTUFfRU5BQkxFOwo+ ICAJCXN3aXRjaCAocGxhbmVfc3RhdGUtPmJhc2UuY3J0Y193KSB7Cj4gZGlmZiAtLWdpdCBhL2Ry aXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRl bF9wbS5jCj4gaW5kZXggMjEzYWQzNS4uM2E3NzA5YyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dw dS9kcm0vaTkxNS9pbnRlbF9wbS5jCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxf cG0uYwo+IEBAIC0zNzg4LDcgKzM3ODgsNyBAQCBzdGF0aWMgdm9pZCBza2xfd3JpdGVfd21fdmFs dWVzKHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwKPiAgCQlza2xfZGlzYWJsZV9z YWd2KGRldl9wcml2KTsKPiAgCj4gIAlmb3JfZWFjaF9pbnRlbF9jcnRjKGRldiwgY3J0Yykgewo+ IC0JCWludCBpLCBsZXZlbCwgbWF4X2xldmVsID0gaWxrX3dtX21heF9sZXZlbChkZXYpOwo+ICsJ CWludCBpOwo+ICAJCWVudW0gcGlwZSBwaXBlID0gY3J0Yy0+cGlwZTsKPiAgCj4gIAkJaWYgKChu ZXctPmRpcnR5X3BpcGVzICYgZHJtX2NydGNfbWFzaygmY3J0Yy0+YmFzZSkpID09IDApCj4gQEAg LTM3OTgsMTkgKzM3OTgsNiBAQCBzdGF0aWMgdm9pZCBza2xfd3JpdGVfd21fdmFsdWVzKHN0cnVj dCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwKPiAgCj4gIAkJSTkxNV9XUklURShQSVBFX1dN X0xJTkVUSU1FKHBpcGUpLCBuZXctPndtX2xpbmV0aW1lW3BpcGVdKTsKPiAgCj4gLQkJZm9yIChs ZXZlbCA9IDA7IGxldmVsIDw9IG1heF9sZXZlbDsgbGV2ZWwrKykgewo+IC0JCQlmb3IgKGkgPSAw OyBpIDwgaW50ZWxfbnVtX3BsYW5lcyhjcnRjKTsgaSsrKQo+IC0JCQkJSTkxNV9XUklURShQTEFO RV9XTShwaXBlLCBpLCBsZXZlbCksCj4gLQkJCQkJICAgbmV3LT5wbGFuZVtwaXBlXVtpXVtsZXZl bF0pOwo+IC0JCQlJOTE1X1dSSVRFKENVUl9XTShwaXBlLCBsZXZlbCksCj4gLQkJCQkgICBuZXct PnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNPUl1bbGV2ZWxdKTsKPiAtCQl9Cj4gLQkJZm9yIChpID0g MDsgaSA8IGludGVsX251bV9wbGFuZXMoY3J0Yyk7IGkrKykKPiAtCQkJSTkxNV9XUklURShQTEFO RV9XTV9UUkFOUyhwaXBlLCBpKSwKPiAtCQkJCSAgIG5ldy0+cGxhbmVfdHJhbnNbcGlwZV1baV0p Owo+IC0JCUk5MTVfV1JJVEUoQ1VSX1dNX1RSQU5TKHBpcGUpLAo+IC0JCQkgICBuZXctPnBsYW5l X3RyYW5zW3BpcGVdW1BMQU5FX0NVUlNPUl0pOwo+IC0KPiAgCQlmb3IgKGkgPSAwOyBpIDwgaW50 ZWxfbnVtX3BsYW5lcyhjcnRjKTsgaSsrKSB7Cj4gIAkJCXNrbF9kZGJfZW50cnlfd3JpdGUoZGV2 X3ByaXYsCj4gIAkJCQkJICAgIFBMQU5FX0JVRl9DRkcocGlwZSwgaSksCj4gLS0gCj4gMi43LjQK PiAKCi0tIApNYXR0IFJvcGVyCkdyYXBoaWNzIFNvZnR3YXJlIEVuZ2luZWVyCklvVEcgUGxhdGZv cm0gRW5hYmxpbmcgJiBEZXZlbG9wbWVudApJbnRlbCBDb3Jwb3JhdGlvbgooOTE2KSAzNTYtMjc5 NQpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1n ZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9s aXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com ([192.55.52.93]:5051 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753075AbcGSRLR (ORCPT ); Tue, 19 Jul 2016 13:11:17 -0400 Date: Tue, 19 Jul 2016 10:10:58 -0700 From: Matt Roper To: Lyude Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Daniel Vetter , Radhakrishna Sripada , Jani Nikula , David Airlie , "open list:INTEL DRM DRIVERS (excluding Poulsbo, Moorestow...), linux-kernel@vger.kernel.org (open list)" Subject: Re: [PATCH 1/2] drm/i915/skl: Update plane watermarks atomically during plane updates Message-ID: <20160719171058.GB21816@intel.com> References: <1468945856-23126-1-git-send-email-cpaul@redhat.com> <1468945856-23126-2-git-send-email-cpaul@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1468945856-23126-2-git-send-email-cpaul@redhat.com> Sender: stable-owner@vger.kernel.org List-ID: On Tue, Jul 19, 2016 at 12:30:55PM -0400, Lyude wrote: > Thanks to Ville for suggesting this as a potential solution to pipe > underruns on Skylake. > > On Skylake all of the registers for configuring planes, including the > registers for configuring their watermarks, are double buffered. New > values written to them won't take effect until said registers are > "armed", which is done by writing to the PLANE_SURF (or in the case of > cursor planes, the CURBASE register) register. > > With this in mind, up until now we've been updating watermarks on skl > like this: > > - Calculate new watermark values in skl_compute_wm() > > - Update non-watermark settings for each plane in > skylake_update_primary_plane()/i9xx_update_cursor() > > - Arm plane registers to update at the start of the next vblank in > skylake_update_primary_plane()/i9xx_update_cursor() > > - *Possibly underrun here, since the plane may now have updated it's > settings using the old and insufficient watermark values* > > - Update watermark settings in skl_write_wm_values() > > - *Possibly underrun here as well if we've passed a vblank, > causing the hardware to get stuck running on intermediate wm values* > > - Finally arm plane registers so they update to the correct values at > the start of the next vblank in skl_wm_flush_pipe() I think you're on the right track with this patch, but I don't think the sequence of events is quite what you describe in the commit message here. The calls to skylake_update_primary_plane()/i9xx_update_cursor() are while we're under vblank evasion, which happens during finish_atomic_commit() -> drm_atomic_helper_commit_planes_on_crtc() Then gen9 watermarks get written during intel_pre_plane_update() for non-modesets or during crtc_enable for modesets. So I believe the actual sequence of events is: non-modeset { - calculate (during atomic check phase) - finish_atomic_commit: - intel_pre_plane_update: - intel_update_watermarks() - {vblank happens; new watermarks + old plane values => underrun } - drm_atomic_helper_commit_planes_on_crtc: - start vblank evasion - write new plane registers - end vblank evasion } or modeset { - calculate (during atomic check phase) - finish_atomic_commit: - crtc_enable: - intel_update_watermarks() - {vblank happens; new watermarks + old plane values => underrun } - drm_atomic_helper_commit_planes_on_crtc: - start vblank evasion - write new plane registers - end vblank evasion } So you're right that fundamentally the problem arises from the watermarks not being updated under vblank evasion when the corresponding plane updates happen (so we might wind up with new watermarks before we've actually switched our plane registers if a vblank sneaks in in the meantime). The sequence is just slightly different from the way you'd listed it out. > > Now we update watermarks atomically like this: > > - Calculate new watermark values in skl_compute_wm() > > - Update watermark values for each plane in > skylake_write_plane_wm()/skylake_write_cursor_wm() > > - Update all the other values for the plane (position, address, etc.) > in skylake_update_primary_plane()/i9xx_update_cursor() Do we also need it in skl_update_plane() (from intel_sprite.c)? > > - Arm plane registers (including the watermark settings) to update at > the start of the next vblank in > skylake_update_primary_plane()/i9xx_update_cursor() > > Which is more of a step in the right direction to fixing all of the > underrun issues we're currently seeing with skl > > Signed-off-by: Lyude Paul > Cc: stable@vger.kernel.org > Cc: Ville Syrj�l� > Cc: Daniel Vetter > Cc: Radhakrishna Sripada > Cc: Hans de Goede > Cc: Matt Roper > --- > drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_pm.c | 15 +----------- > 2 files changed, 48 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index fb7d8fc5..3d2c125 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2971,6 +2971,27 @@ u32 skl_plane_ctl_rotation(unsigned int rotation) > return 0; > } > > +static void skylake_write_plane_wm(struct intel_crtc *intel_crtc, > + int plane) > +{ > + struct drm_crtc *crtc = &intel_crtc->base; > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = to_i915(dev); > + struct skl_wm_values *wm = &dev_priv->wm.skl_results; > + int level, max_level = ilk_wm_max_level(dev); > + enum pipe pipe = intel_crtc->pipe; > + > + mutex_lock(&dev_priv->wm.wm_mutex); I don't think this mutex is actually protecting anything important here is it? We already have the crtc & plane mutexes and we're not really using/touching any global state. Actually, we're calling this while under vblank evasion, so we're not allowed to sleep here anyway. (same comment for the cursor version) Matt > + > + for (level = 0; level < max_level; level++) { > + I915_WRITE(PLANE_WM(pipe, plane, level), > + wm->plane[pipe][plane][level]); > + } > + I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]); > + > + mutex_unlock(&dev_priv->wm.wm_mutex); > +} > + > static void skylake_update_primary_plane(struct drm_plane *plane, > const struct intel_crtc_state *crtc_state, > const struct intel_plane_state *plane_state) > @@ -3031,6 +3052,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane, > intel_crtc->adjusted_x = x_offset; > intel_crtc->adjusted_y = y_offset; > > + skylake_write_plane_wm(intel_crtc, 0); > + > I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); > I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); > I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); > @@ -10233,6 +10256,27 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base, > } > } > > +static void skl_write_cursor_wm(struct intel_crtc *intel_crtc) > +{ > + struct drm_crtc *crtc = &intel_crtc->base; > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = to_i915(dev); > + struct skl_wm_values *wm = &dev_priv->wm.skl_results; > + int level, max_level = ilk_wm_max_level(dev); > + enum pipe pipe = intel_crtc->pipe; > + > + mutex_lock(&dev_priv->wm.wm_mutex); > + > + for (level = 0; level <= max_level; level++) { > + I915_WRITE(CUR_WM(pipe, level), > + wm->plane[pipe][PLANE_CURSOR][level]); > + } > + I915_WRITE(CUR_WM_TRANS(pipe), > + wm->plane_trans[pipe][PLANE_CURSOR]); > + > + mutex_unlock(&dev_priv->wm.wm_mutex); > +} > + > static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, > const struct intel_plane_state *plane_state) > { > @@ -10242,6 +10286,9 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, > int pipe = intel_crtc->pipe; > uint32_t cntl = 0; > > + if (IS_SKYLAKE(dev_priv)) > + skl_write_cursor_wm(intel_crtc); > + > if (plane_state && plane_state->visible) { > cntl = MCURSOR_GAMMA_ENABLE; > switch (plane_state->base.crtc_w) { > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 213ad35..3a7709c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3788,7 +3788,7 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, > skl_disable_sagv(dev_priv); > > for_each_intel_crtc(dev, crtc) { > - int i, level, max_level = ilk_wm_max_level(dev); > + int i; > enum pipe pipe = crtc->pipe; > > if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0) > @@ -3798,19 +3798,6 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, > > I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); > > - for (level = 0; level <= max_level; level++) { > - for (i = 0; i < intel_num_planes(crtc); i++) > - I915_WRITE(PLANE_WM(pipe, i, level), > - new->plane[pipe][i][level]); > - I915_WRITE(CUR_WM(pipe, level), > - new->plane[pipe][PLANE_CURSOR][level]); > - } > - for (i = 0; i < intel_num_planes(crtc); i++) > - I915_WRITE(PLANE_WM_TRANS(pipe, i), > - new->plane_trans[pipe][i]); > - I915_WRITE(CUR_WM_TRANS(pipe), > - new->plane_trans[pipe][PLANE_CURSOR]); > - > for (i = 0; i < intel_num_planes(crtc); i++) { > skl_ddb_entry_write(dev_priv, > PLANE_BUF_CFG(pipe, i), > -- > 2.7.4 > -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795