Re: [Qemu-devel] [PATCH v4 00/15] POWER9 TCG enablements - part1

[David Gibson <david@gibson.dropbear.id.au>]

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On Tue, Jul 26, 2016 at 05:28:23PM +0530, Nikunj A Dadhania wrote:
> This set starts adding new instructions for POWER9 described in ISA3.0.
> 
> Patches:
>   01-02: First two patches adds the required POWER9 cpu model and ISA defines.
>   03-14: Adds following instructions:
>              addpcis   : Add PC Immediate Shifted
>              cmprb     : Compare Ranged Byte
>              moduw     : Modulo Unsigned Word
>              modsw     : Modulo Signed Word
>              modud     : Modulo Unsigned Dword
>              modsd     : Modulo Signed Dword
>              cnttzd[.] : Count Trailing Zero Dword
>              cnttzw[.] : Count Trailing Zero Word
>              cmpeqb    : Compare Equal Byte
>              setb      : Set Boolean
>              maddld    : Multiply-Add Low Dword
>              maddhd    : Multiply-Add High Dword
>              maddhdu   : Multiply-Add High Dword Unsigned
>          Changes following instructions:
>              divd[u][o][.]: Divide Doubleword Signed/Unsigned
>              divw[u][o][.]: Divide Word Signed/Unsigned
>      15: Adds support for the new Expanded Opcode (EO) added in
>   ISA3.0

I've applied these to ppc-for-2.8, except for the div rework which I
have a comment on, and for which I'm hoping for an R-b from rth.  I
did make a small tweak to 1/15.

> 
> Changelog:
> v3:
> * Accumulate summary overflow in place of over-writing in div[w,d] operations
> 
> v2: 
> * Implement branchless modulo instruction
> * Change divd and divw to branchless implementation similar to modulo
>   instructions
> * Drop MMU_3_00 defines from the POWER9 define until radix support is
>   added.
> 
> v1:
> * addpcis - shift the immediate before adding
> * cmprb logic without branches
> * mod[su][wd]: use helpers
> * cmpeqb - use bit magics in the helpers
> * setb - bug fix and branchless
> * maddld - discard multiple dword calculation as we need only lower 64-bit
> * Expanded opcode - drop pad from 32-bit and free the third level indirect 
>   table in unrealize
> 
> Aneesh Kumar K.V (1):
>   target-ppc: Introduce Power9 family
> 
> Nikunj A Dadhania (12):
>   target-ppc: Introduce POWER ISA 3.0 flag
>   target-ppc: adding addpcis instruction
>   target-ppc: add cmprb instruction
>   target-ppc: add modulo word operations
>   target-ppc: add modulo dword operations
>   target-ppc: implement branch-less divw[o][.]
>   target-ppc: implement branch-less divd[o][.]
>   target-ppc: add cnttzw[.] instruction
>   target-ppc: add cmpeqb instruction
>   target-ppc: add maddld instruction
>   target-ppc: add maddhd and maddhdu instruction
>   target-ppc: introduce opc4 for Expanded Opcode
> 
> Sandipan Das (1):
>   target-ppc: add cnttzd[.] instruction
> 
> Vivek Andrew Sha (1):
>   target-ppc: add setb instruction
> 
>  hw/ppc/spapr_cpu_core.c     |   5 +
>  target-ppc/cpu-models.c     |   5 +
>  target-ppc/cpu-models.h     |   1 +
>  target-ppc/cpu-qom.h        |   1 +
>  target-ppc/cpu.h            |   5 +-
>  target-ppc/helper.h         |   3 +
>  target-ppc/int_helper.c     |  32 ++++
>  target-ppc/mmu_helper.c     |   2 +-
>  target-ppc/translate.c      | 432 +++++++++++++++++++++++++++++++++++++-------
>  target-ppc/translate_init.c | 212 ++++++++++++++++++----
>  10 files changed, 594 insertions(+), 104 deletions(-)
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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