From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mihai =?UTF-8?B?RG9uyJt1?= Subject: Re: [PATCH v3 2/3] x86/emulate: add support of emulating SSE2 instruction {, v}movd mm, r32/m32 and {, v}movq mm, r64 Date: Mon, 1 Aug 2016 18:10:51 +0300 Message-ID: <20160801181051.547a4b4e@bitdefender.com> References: <20160801025231.7211-1-mdontu@bitdefender.com> <20160801025231.7211-2-mdontu@bitdefender.com> <96929bbb-22f5-4e58-648f-a734caea2ee6@citrix.com> <20160801155327.18e0e54c@bitdefender.com> <579F63BC02000078001014A8@prv-mh.provo.novell.com> <20160801162821.58a728a9@bitdefender.com> <579F6E180200007800101552@prv-mh.provo.novell.com> <20160801174833.5a20f846@bitdefender.com> <82a9354b-8a21-da20-634f-094b9162847c@citrix.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============3031121155721472246==" Return-path: In-Reply-To: <82a9354b-8a21-da20-634f-094b9162847c@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: Andrew Cooper Cc: Zhi Wang , Jan Beulich , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org --===============3031121155721472246== Content-Type: multipart/signed; micalg=pgp-sha1; boundary="Sig_/KWZ6rKep0SMqV.ma__Qyod2"; protocol="application/pgp-signature" --Sig_/KWZ6rKep0SMqV.ma__Qyod2 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Monday 01 August 2016 15:53:56 Andrew Cooper wrote: > On 01/08/16 15:48, Mihai Don=C8=9Bu wrote: > > > I'd rather pick a fixed register and update the regs->... field from = that > > > after the stub was executed. E.g. using rAX and treating it just like= a > > > return value of the "call". But maybe I'm imagining this easier than = it > > > really is; as an alternative I'd then suggest really following what A= ndrew > > > said - use a pointer into regs->, not mmvalp. But (as said in the rev= iew > > > mail) you'd then have the problem of the missing zero-extension for > > > writes to 32-bit GPRs > >=20 > > I thought that by re-using (hijacking, really) mmvalp, the patch will > > look less intrusive and thus not add too much to an already complex > > code. > > > > Assuming I'll just pass to the stub "a"(ea.reg), would it be a good > > idea to just zero-out the 64bit register before that? It does not > > appear to be any instructions that write just the low dword. Or am I > > misunderstanding the zero-extension concept? =20 >=20 > Any write to a 32bit GPR zero extends it to 64 bits. This is specified > by AMD64 and only applies to 32bit writes. 8 and 16 bit writes leave > the upper bits alone. >=20 > Therefore movd %mm, %eax will move 32bits from %mm to eax, then zero > extend the upper 32 bits of %rax. ... and given that the stub has (%rAX) as destination, the zero-extension is not implicit and I have to do it myself. Which also means two of my tests in a previous patch are wrong (0xbdbdbdbdffffffff checks). Darn! :-) --=20 Mihai DON=C8=9AU --Sig_/KWZ6rKep0SMqV.ma__Qyod2 Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlefZnsACgkQfOUeqrYRMKo38gCghnJeh1jERJkA5V+ppO0bqbzG 72oAnREBKsdyl1Hg7QvCBYsUAenenwXN =HCnt -----END PGP SIGNATURE----- --Sig_/KWZ6rKep0SMqV.ma__Qyod2-- --===============3031121155721472246== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5v cmcveGVuLWRldmVsCg== --===============3031121155721472246==--