From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH 0197/1285] Replace numeric parameter like 0444 with macro Date: Tue, 2 Aug 2016 14:37:37 +0300 Message-ID: <20160802113737.GT4329@intel.com> References: <20160802104847.26886-1-baolex.ni@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20160802104847.26886-1-baolex.ni@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Baole Ni Cc: wuninsu@gmail.com, k.kozlowski@samsung.com, treding@nvidia.com, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, kyungmin.park@samsung.com, kgene@kernel.org, bp@alien8.de, dri-devel@lists.freedesktop.org, dougthompson@xmission.com, daniel.vetter@intel.com, chuansheng.liu@intel.com List-Id: dri-devel@lists.freedesktop.org T24gVHVlLCBBdWcgMDIsIDIwMTYgYXQgMDY6NDg6NDdQTSArMDgwMCwgQmFvbGUgTmkgd3JvdGU6 Cj4gSSBmaW5kIHRoYXQgdGhlIGRldmVsb3BlcnMgb2Z0ZW4ganVzdCBzcGVjaWZpZWQgdGhlIG51 bWVyaWMgdmFsdWUKPiB3aGVuIGNhbGxpbmcgYSBtYWNybyB3aGljaCBpcyBkZWZpbmVkIHdpdGgg YSBwYXJhbWV0ZXIgZm9yIGFjY2VzcyBwZXJtaXNzaW9uLgo+IEFzIHdlIGtub3csIHRoZXNlIG51 bWVyaWMgdmFsdWUgZm9yIGFjY2VzcyBwZXJtaXNzaW9uIGhhdmUgaGFkIHRoZSBjb3JyZXNwb25k aW5nIG1hY3JvLAo+IGFuZCB0aGF0IHVzaW5nIG1hY3JvIGNhbiBpbXByb3ZlIHRoZSByb2J1c3Ru ZXNzIGFuZCByZWFkYWJpbGl0eSBvZiB0aGUgY29kZSwKPiB0aHVzLCBJIHN1Z2dlc3QgcmVwbGFj aW5nIHRoZSBudW1lcmljIHBhcmFtZXRlciB3aXRoIHRoZSBtYWNyby4KPiAKPiBTaWduZWQtb2Zm LWJ5OiBDaHVhbnNoZW5nIExpdSA8Y2h1YW5zaGVuZy5saXVAaW50ZWwuY29tPgo+IFNpZ25lZC1v ZmYtYnk6IEJhb2xlIE5pIDxiYW9sZXgubmlAaW50ZWwuY29tPgo+IC0tLQo+ICBkcml2ZXJzL2dw dS9kcm0vaTkxNS9pOTE1X3BhcmFtcy5jIHwgNjQgKysrKysrKysrKysrKysrKysrKy0tLS0tLS0t LS0tLS0tLS0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDMyIGluc2VydGlvbnMoKyksIDMyIGRlbGV0 aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3BhcmFt cy5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9wYXJhbXMuYwo+IGluZGV4IDE3NzlmMDIu LjcxODRlMDYgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9wYXJhbXMu Ywo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcGFyYW1zLmMKPiBAQCAtNjAsMjIg KzYwLDIyIEBAIHN0cnVjdCBpOTE1X3BhcmFtcyBpOTE1IF9fcmVhZF9tb3N0bHkgPSB7Cj4gIAku aW5qZWN0X2xvYWRfZmFpbHVyZSA9IDAsCj4gIH07Cj4gIAo+IC1tb2R1bGVfcGFyYW1fbmFtZWQo bW9kZXNldCwgaTkxNS5tb2Rlc2V0LCBpbnQsIDA0MDApOwo+ICttb2R1bGVfcGFyYW1fbmFtZWQo bW9kZXNldCwgaTkxNS5tb2Rlc2V0LCBpbnQsIFNfSVJVU1IpOwoKQXQgbGVhc3QgSSBjYW4ndCBy ZWFkIHRob3NlIG1hY3Jvcy4gT2N0YWwgaXMgbXVjaCBjbGVhcmVyIElNTy4KCj4gIE1PRFVMRV9Q QVJNX0RFU0MobW9kZXNldCwKPiAgCSJVc2Uga2VybmVsIG1vZGVzZXR0aW5nIFtLTVNdICgwPWRp c2FibGUsICIKPiAgCSIxPW9uLCAtMT1mb3JjZSB2Z2EgY29uc29sZSBwcmVmZXJlbmNlIFtkZWZh dWx0XSkiKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUocGFuZWxfaWdub3JlX2xp ZCwgaTkxNS5wYW5lbF9pZ25vcmVfbGlkLCBpbnQsIDA2MDApOwo+ICttb2R1bGVfcGFyYW1fbmFt ZWRfdW5zYWZlKHBhbmVsX2lnbm9yZV9saWQsIGk5MTUucGFuZWxfaWdub3JlX2xpZCwgaW50LCBT X0lSVVNSIHwgU19JV1VTUik7Cj4gIE1PRFVMRV9QQVJNX0RFU0MocGFuZWxfaWdub3JlX2xpZCwK PiAgCSJPdmVycmlkZSBsaWQgc3RhdHVzICgwPWF1dG9kZXRlY3QsIDE9YXV0b2RldGVjdCBkaXNh YmxlZCBbZGVmYXVsdF0sICIKPiAgCSItMT1mb3JjZSBsaWQgY2xvc2VkLCAtMj1mb3JjZSBsaWQg b3BlbikiKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoc2VtYXBob3JlcywgaTkx NS5zZW1hcGhvcmVzLCBpbnQsIDA0MDApOwo+ICttb2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKHNl bWFwaG9yZXMsIGk5MTUuc2VtYXBob3JlcywgaW50LCBTX0lSVVNSKTsKPiAgTU9EVUxFX1BBUk1f REVTQyhzZW1hcGhvcmVzLAo+ICAJIlVzZSBzZW1hcGhvcmVzIGZvciBpbnRlci1yaW5nIHN5bmMg Igo+ICAJIihkZWZhdWx0OiAtMSAodXNlIHBlci1jaGlwIGRlZmF1bHRzKSkiKTsKPiAgCj4gLW1v ZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoZW5hYmxlX3JjNiwgaTkxNS5lbmFibGVfcmM2LCBpbnQs IDA0MDApOwo+ICttb2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKGVuYWJsZV9yYzYsIGk5MTUuZW5h YmxlX3JjNiwgaW50LCBTX0lSVVNSKTsKPiAgTU9EVUxFX1BBUk1fREVTQyhlbmFibGVfcmM2LAo+ ICAJIkVuYWJsZSBwb3dlci1zYXZpbmcgcmVuZGVyIEMtc3RhdGUgNi4gIgo+ICAJIkRpZmZlcmVu dCBzdGFnZXMgY2FuIGJlIHNlbGVjdGVkIHZpYSBiaXRtYXNrIHZhbHVlcyAiCj4gQEAgLTgzLDgy ICs4Myw4MiBAQCBNT0RVTEVfUEFSTV9ERVNDKGVuYWJsZV9yYzYsCj4gIAkiRm9yIGV4YW1wbGUs IDMgd291bGQgZW5hYmxlIHJjNiBhbmQgZGVlcCByYzYsIGFuZCA3IHdvdWxkIGVuYWJsZSBldmVy eXRoaW5nLiAiCj4gIAkiZGVmYXVsdDogLTEgKHVzZSBwZXItY2hpcCBkZWZhdWx0KSIpOwo+ICAK PiAtbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZShlbmFibGVfZGMsIGk5MTUuZW5hYmxlX2RjLCBp bnQsIDA0MDApOwo+ICttb2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKGVuYWJsZV9kYywgaTkxNS5l bmFibGVfZGMsIGludCwgU19JUlVTUik7Cj4gIE1PRFVMRV9QQVJNX0RFU0MoZW5hYmxlX2RjLAo+ ICAJIkVuYWJsZSBwb3dlci1zYXZpbmcgZGlzcGxheSBDLXN0YXRlcy4gIgo+ICAJIigtMT1hdXRv IFtkZWZhdWx0XTsgMD1kaXNhYmxlOyAxPXVwIHRvIERDNTsgMj11cCB0byBEQzYpIik7Cj4gIAo+ IC1tb2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKGVuYWJsZV9mYmMsIGk5MTUuZW5hYmxlX2ZiYywg aW50LCAwNjAwKTsKPiArbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZShlbmFibGVfZmJjLCBpOTE1 LmVuYWJsZV9mYmMsIGludCwgU19JUlVTUiB8IFNfSVdVU1IpOwo+ICBNT0RVTEVfUEFSTV9ERVND KGVuYWJsZV9mYmMsCj4gIAkiRW5hYmxlIGZyYW1lIGJ1ZmZlciBjb21wcmVzc2lvbiBmb3IgcG93 ZXIgc2F2aW5ncyAiCj4gIAkiKGRlZmF1bHQ6IC0xICh1c2UgcGVyLWNoaXAgZGVmYXVsdCkpIik7 Cj4gIAo+IC1tb2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKGx2ZHNfY2hhbm5lbF9tb2RlLCBpOTE1 Lmx2ZHNfY2hhbm5lbF9tb2RlLCBpbnQsIDA0MDApOwo+ICttb2R1bGVfcGFyYW1fbmFtZWRfdW5z YWZlKGx2ZHNfY2hhbm5lbF9tb2RlLCBpOTE1Lmx2ZHNfY2hhbm5lbF9tb2RlLCBpbnQsIFNfSVJV U1IpOwo+ICBNT0RVTEVfUEFSTV9ERVNDKGx2ZHNfY2hhbm5lbF9tb2RlLAo+ICAJICJTcGVjaWZ5 IExWRFMgY2hhbm5lbCBtb2RlICIKPiAgCSAiKDA9cHJvYmUgQklPUyBbZGVmYXVsdF0sIDE9c2lu Z2xlLWNoYW5uZWwsIDI9ZHVhbC1jaGFubmVsKSIpOwo+ICAKPiAtbW9kdWxlX3BhcmFtX25hbWVk X3Vuc2FmZShsdmRzX3VzZV9zc2MsIGk5MTUucGFuZWxfdXNlX3NzYywgaW50LCAwNjAwKTsKPiAr bW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZShsdmRzX3VzZV9zc2MsIGk5MTUucGFuZWxfdXNlX3Nz YywgaW50LCBTX0lSVVNSIHwgU19JV1VTUik7Cj4gIE1PRFVMRV9QQVJNX0RFU0MobHZkc191c2Vf c3NjLAo+ICAJIlVzZSBTcHJlYWQgU3BlY3RydW0gQ2xvY2sgd2l0aCBwYW5lbHMgW0xWRFMvZURQ XSAiCj4gIAkiKGRlZmF1bHQ6IGF1dG8gZnJvbSBWQlQpIik7Cj4gIAo+IC1tb2R1bGVfcGFyYW1f bmFtZWRfdW5zYWZlKHZidF9zZHZvX3BhbmVsX3R5cGUsIGk5MTUudmJ0X3Nkdm9fcGFuZWxfdHlw ZSwgaW50LCAwNDAwKTsKPiArbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZSh2YnRfc2R2b19wYW5l bF90eXBlLCBpOTE1LnZidF9zZHZvX3BhbmVsX3R5cGUsIGludCwgU19JUlVTUik7Cj4gIE1PRFVM RV9QQVJNX0RFU0ModmJ0X3Nkdm9fcGFuZWxfdHlwZSwKPiAgCSJPdmVycmlkZS9JZ25vcmUgc2Vs ZWN0aW9uIG9mIFNEVk8gcGFuZWwgbW9kZSBpbiB0aGUgVkJUICIKPiAgCSIoLTI9aWdub3JlLCAt MT1hdXRvIFtkZWZhdWx0XSwgaW5kZXggaW4gVkJUIEJJT1MgdGFibGUpIik7Cj4gIAo+IC1tb2R1 bGVfcGFyYW1fbmFtZWRfdW5zYWZlKHJlc2V0LCBpOTE1LnJlc2V0LCBib29sLCAwNjAwKTsKPiAr bW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZShyZXNldCwgaTkxNS5yZXNldCwgYm9vbCwgU19JUlVT UiB8IFNfSVdVU1IpOwo+ICBNT0RVTEVfUEFSTV9ERVNDKHJlc2V0LCAiQXR0ZW1wdCBHUFUgcmVz ZXRzIChkZWZhdWx0OiB0cnVlKSIpOwo+ICAKPiAtbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZShl bmFibGVfaGFuZ2NoZWNrLCBpOTE1LmVuYWJsZV9oYW5nY2hlY2ssIGJvb2wsIDA2NDQpOwo+ICtt b2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKGVuYWJsZV9oYW5nY2hlY2ssIGk5MTUuZW5hYmxlX2hh bmdjaGVjaywgYm9vbCwgU19JUlVTUiB8IFNfSVdVU1IgfCBTX0lSR1JQIHwgU19JUk9USCk7Cj4g IE1PRFVMRV9QQVJNX0RFU0MoZW5hYmxlX2hhbmdjaGVjaywKPiAgCSJQZXJpb2RpY2FsbHkgY2hl Y2sgR1BVIGFjdGl2aXR5IGZvciBkZXRlY3RpbmcgaGFuZ3MuICIKPiAgCSJXQVJOSU5HOiBEaXNh YmxpbmcgdGhpcyBjYW4gY2F1c2Ugc3lzdGVtIHdpZGUgaGFuZ3MuICIKPiAgCSIoZGVmYXVsdDog dHJ1ZSkiKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoZW5hYmxlX3BwZ3R0LCBp OTE1LmVuYWJsZV9wcGd0dCwgaW50LCAwNDAwKTsKPiArbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2Fm ZShlbmFibGVfcHBndHQsIGk5MTUuZW5hYmxlX3BwZ3R0LCBpbnQsIFNfSVJVU1IpOwo+ICBNT0RV TEVfUEFSTV9ERVNDKGVuYWJsZV9wcGd0dCwKPiAgCSJPdmVycmlkZSBQUEdUVCB1c2FnZS4gIgo+ ICAJIigtMT1hdXRvIFtkZWZhdWx0XSwgMD1kaXNhYmxlZCwgMT1hbGlhc2luZywgMj1mdWxsLCAz PWZ1bGwgd2l0aCBleHRlbmRlZCBhZGRyZXNzIHNwYWNlKSIpOwo+ICAKPiAtbW9kdWxlX3BhcmFt X25hbWVkX3Vuc2FmZShlbmFibGVfZXhlY2xpc3RzLCBpOTE1LmVuYWJsZV9leGVjbGlzdHMsIGlu dCwgMDQwMCk7Cj4gK21vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoZW5hYmxlX2V4ZWNsaXN0cywg aTkxNS5lbmFibGVfZXhlY2xpc3RzLCBpbnQsIFNfSVJVU1IpOwo+ICBNT0RVTEVfUEFSTV9ERVND KGVuYWJsZV9leGVjbGlzdHMsCj4gIAkiT3ZlcnJpZGUgZXhlY2xpc3RzIHVzYWdlLiAiCj4gIAki KC0xPWF1dG8gW2RlZmF1bHRdLCAwPWRpc2FibGVkLCAxPWVuYWJsZWQpIik7Cj4gIAo+IC1tb2R1 bGVfcGFyYW1fbmFtZWRfdW5zYWZlKGVuYWJsZV9wc3IsIGk5MTUuZW5hYmxlX3BzciwgaW50LCAw NjAwKTsKPiArbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZShlbmFibGVfcHNyLCBpOTE1LmVuYWJs ZV9wc3IsIGludCwgU19JUlVTUiB8IFNfSVdVU1IpOwo+ICBNT0RVTEVfUEFSTV9ERVNDKGVuYWJs ZV9wc3IsICJFbmFibGUgUFNSICIKPiAgCQkgIigwPWRpc2FibGVkLCAxPWVuYWJsZWQgLSBsaW5r IG1vZGUgY2hvc2VuIHBlci1wbGF0Zm9ybSwgMj1mb3JjZSBsaW5rLXN0YW5kYnkgbW9kZSwgMz1m b3JjZSBsaW5rLW9mZiBtb2RlKSAiCj4gIAkJICJEZWZhdWx0OiAtMSAodXNlIHBlci1jaGlwIGRl ZmF1bHQpIik7Cj4gIAo+IC1tb2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKHByZWxpbWluYXJ5X2h3 X3N1cHBvcnQsIGk5MTUucHJlbGltaW5hcnlfaHdfc3VwcG9ydCwgaW50LCAwNDAwKTsKPiArbW9k dWxlX3BhcmFtX25hbWVkX3Vuc2FmZShwcmVsaW1pbmFyeV9od19zdXBwb3J0LCBpOTE1LnByZWxp bWluYXJ5X2h3X3N1cHBvcnQsIGludCwgU19JUlVTUik7Cj4gIE1PRFVMRV9QQVJNX0RFU0MocHJl bGltaW5hcnlfaHdfc3VwcG9ydCwKPiAgCSJFbmFibGUgcHJlbGltaW5hcnkgaGFyZHdhcmUgc3Vw cG9ydC4iKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoZGlzYWJsZV9wb3dlcl93 ZWxsLCBpOTE1LmRpc2FibGVfcG93ZXJfd2VsbCwgaW50LCAwNDAwKTsKPiArbW9kdWxlX3BhcmFt X25hbWVkX3Vuc2FmZShkaXNhYmxlX3Bvd2VyX3dlbGwsIGk5MTUuZGlzYWJsZV9wb3dlcl93ZWxs LCBpbnQsIFNfSVJVU1IpOwo+ICBNT0RVTEVfUEFSTV9ERVNDKGRpc2FibGVfcG93ZXJfd2VsbCwK PiAgCSJEaXNhYmxlIGRpc3BsYXkgcG93ZXIgd2VsbHMgd2hlbiBwb3NzaWJsZSAiCj4gIAkiKC0x PWF1dG8gW2RlZmF1bHRdLCAwPXBvd2VyIHdlbGxzIGFsd2F5cyBvbiwgMT1wb3dlciB3ZWxscyBk aXNhYmxlZCB3aGVuIHBvc3NpYmxlKSIpOwo+ICAKPiAtbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2Fm ZShlbmFibGVfaXBzLCBpOTE1LmVuYWJsZV9pcHMsIGludCwgMDYwMCk7Cj4gK21vZHVsZV9wYXJh bV9uYW1lZF91bnNhZmUoZW5hYmxlX2lwcywgaTkxNS5lbmFibGVfaXBzLCBpbnQsIFNfSVJVU1Ig fCBTX0lXVVNSKTsKPiAgTU9EVUxFX1BBUk1fREVTQyhlbmFibGVfaXBzLCAiRW5hYmxlIElQUyAo ZGVmYXVsdDogdHJ1ZSkiKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZChmYXN0Ym9vdCwgaTkx NS5mYXN0Ym9vdCwgYm9vbCwgMDYwMCk7Cj4gK21vZHVsZV9wYXJhbV9uYW1lZChmYXN0Ym9vdCwg aTkxNS5mYXN0Ym9vdCwgYm9vbCwgU19JUlVTUiB8IFNfSVdVU1IpOwo+ICBNT0RVTEVfUEFSTV9E RVNDKGZhc3Rib290LAo+ICAJIlRyeSB0byBza2lwIHVubmVjZXNzYXJ5IG1vZGUgc2V0cyBhdCBi b290IHRpbWUgKGRlZmF1bHQ6IGZhbHNlKSIpOwo+ICAKPiAtbW9kdWxlX3BhcmFtX25hbWVkX3Vu c2FmZShwcmVmYXVsdF9kaXNhYmxlLCBpOTE1LnByZWZhdWx0X2Rpc2FibGUsIGJvb2wsIDA2MDAp Owo+ICttb2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKHByZWZhdWx0X2Rpc2FibGUsIGk5MTUucHJl ZmF1bHRfZGlzYWJsZSwgYm9vbCwgU19JUlVTUiB8IFNfSVdVU1IpOwo+ICBNT0RVTEVfUEFSTV9E RVNDKHByZWZhdWx0X2Rpc2FibGUsCj4gIAkiRGlzYWJsZSBwYWdlIHByZWZhdWx0aW5nIGZvciBw cmVhZC9wd3JpdGUvcmVsb2MgKGRlZmF1bHQ6ZmFsc2UpLiAiCj4gIAkiRm9yIGRldmVsb3BlcnMg b25seS4iKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUobG9hZF9kZXRlY3RfdGVz dCwgaTkxNS5sb2FkX2RldGVjdF90ZXN0LCBib29sLCAwNjAwKTsKPiArbW9kdWxlX3BhcmFtX25h bWVkX3Vuc2FmZShsb2FkX2RldGVjdF90ZXN0LCBpOTE1LmxvYWRfZGV0ZWN0X3Rlc3QsIGJvb2ws IFNfSVJVU1IgfCBTX0lXVVNSKTsKPiAgTU9EVUxFX1BBUk1fREVTQyhsb2FkX2RldGVjdF90ZXN0 LAo+ICAJIkZvcmNlLWVuYWJsZSB0aGUgVkdBIGxvYWQgZGV0ZWN0IGNvZGUgZm9yIHRlc3Rpbmcg KGRlZmF1bHQ6ZmFsc2UpLiAiCj4gIAkiRm9yIGRldmVsb3BlcnMgb25seS4iKTsKPiAgCj4gLW1v ZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoaW52ZXJ0X2JyaWdodG5lc3MsIGk5MTUuaW52ZXJ0X2Jy aWdodG5lc3MsIGludCwgMDYwMCk7Cj4gK21vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoaW52ZXJ0 X2JyaWdodG5lc3MsIGk5MTUuaW52ZXJ0X2JyaWdodG5lc3MsIGludCwgU19JUlVTUiB8IFNfSVdV U1IpOwo+ICBNT0RVTEVfUEFSTV9ERVNDKGludmVydF9icmlnaHRuZXNzLAo+ICAJIkludmVydCBi YWNrbGlnaHQgYnJpZ2h0bmVzcyAiCj4gIAkiKC0xIGZvcmNlIG5vcm1hbCwgMCBtYWNoaW5lIGRl ZmF1bHRzLCAxIGZvcmNlIGludmVyc2lvbiksIHBsZWFzZSAiCj4gQEAgLTE2Niw0NyArMTY2LDQ3 IEBAIE1PRFVMRV9QQVJNX0RFU0MoaW52ZXJ0X2JyaWdodG5lc3MsCj4gIAkidG8gZHJpLWRldmVs QGxpc3RzLmZyZWVkZXNrdG9wLm9yZywgaWYgeW91ciBtYWNoaW5lIG5lZWRzIGl0LiAiCj4gIAki SXQgd2lsbCB0aGVuIGJlIGluY2x1ZGVkIGluIGFuIHVwY29taW5nIG1vZHVsZSB2ZXJzaW9uLiIp Owo+ICAKPiAtbW9kdWxlX3BhcmFtX25hbWVkKGRpc2FibGVfZGlzcGxheSwgaTkxNS5kaXNhYmxl X2Rpc3BsYXksIGJvb2wsIDA0MDApOwo+ICttb2R1bGVfcGFyYW1fbmFtZWQoZGlzYWJsZV9kaXNw bGF5LCBpOTE1LmRpc2FibGVfZGlzcGxheSwgYm9vbCwgU19JUlVTUik7Cj4gIE1PRFVMRV9QQVJN X0RFU0MoZGlzYWJsZV9kaXNwbGF5LCAiRGlzYWJsZSBkaXNwbGF5IChkZWZhdWx0OiBmYWxzZSki KTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoZW5hYmxlX2NtZF9wYXJzZXIsIGk5 MTUuZW5hYmxlX2NtZF9wYXJzZXIsIGludCwgMDYwMCk7Cj4gK21vZHVsZV9wYXJhbV9uYW1lZF91 bnNhZmUoZW5hYmxlX2NtZF9wYXJzZXIsIGk5MTUuZW5hYmxlX2NtZF9wYXJzZXIsIGludCwgU19J UlVTUiB8IFNfSVdVU1IpOwo+ICBNT0RVTEVfUEFSTV9ERVNDKGVuYWJsZV9jbWRfcGFyc2VyLAo+ ICAJCSAiRW5hYmxlIGNvbW1hbmQgcGFyc2luZyAoMT1lbmFibGVkIFtkZWZhdWx0XSwgMD1kaXNh YmxlZCkiKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUodXNlX21taW9fZmxpcCwg aTkxNS51c2VfbW1pb19mbGlwLCBpbnQsIDA2MDApOwo+ICttb2R1bGVfcGFyYW1fbmFtZWRfdW5z YWZlKHVzZV9tbWlvX2ZsaXAsIGk5MTUudXNlX21taW9fZmxpcCwgaW50LCBTX0lSVVNSIHwgU19J V1VTUik7Cj4gIE1PRFVMRV9QQVJNX0RFU0ModXNlX21taW9fZmxpcCwKPiAgCQkgInVzZSBNTUlP IGZsaXBzICgtMT1uZXZlciwgMD1kcml2ZXIgZGlzY3JldGlvbiBbZGVmYXVsdF0sIDE9YWx3YXlz KSIpOwo+ICAKPiAtbW9kdWxlX3BhcmFtX25hbWVkKG1taW9fZGVidWcsIGk5MTUubW1pb19kZWJ1 ZywgaW50LCAwNjAwKTsKPiArbW9kdWxlX3BhcmFtX25hbWVkKG1taW9fZGVidWcsIGk5MTUubW1p b19kZWJ1ZywgaW50LCBTX0lSVVNSIHwgU19JV1VTUik7Cj4gIE1PRFVMRV9QQVJNX0RFU0MobW1p b19kZWJ1ZywKPiAgCSJFbmFibGUgdGhlIE1NSU8gZGVidWcgY29kZSBmb3IgdGhlIGZpcnN0IE4g ZmFpbHVyZXMgKGRlZmF1bHQ6IG9mZikuICIKPiAgCSJUaGlzIG1heSBuZWdhdGl2ZWx5IGFmZmVj dCBwZXJmb3JtYW5jZS4iKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZCh2ZXJib3NlX3N0YXRl X2NoZWNrcywgaTkxNS52ZXJib3NlX3N0YXRlX2NoZWNrcywgYm9vbCwgMDYwMCk7Cj4gK21vZHVs ZV9wYXJhbV9uYW1lZCh2ZXJib3NlX3N0YXRlX2NoZWNrcywgaTkxNS52ZXJib3NlX3N0YXRlX2No ZWNrcywgYm9vbCwgU19JUlVTUiB8IFNfSVdVU1IpOwo+ICBNT0RVTEVfUEFSTV9ERVNDKHZlcmJv c2Vfc3RhdGVfY2hlY2tzLAo+ICAJIkVuYWJsZSB2ZXJib3NlIGxvZ3MgKGllLiBXQVJOX09OKCkp IGluIGNhc2Ugb2YgdW5leHBlY3RlZCBodyBzdGF0ZSBjb25kaXRpb25zLiIpOwo+ICAKPiAtbW9k dWxlX3BhcmFtX25hbWVkX3Vuc2FmZShudWNsZWFyX3BhZ2VmbGlwLCBpOTE1Lm51Y2xlYXJfcGFn ZWZsaXAsIGJvb2wsIDA2MDApOwo+ICttb2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKG51Y2xlYXJf cGFnZWZsaXAsIGk5MTUubnVjbGVhcl9wYWdlZmxpcCwgYm9vbCwgU19JUlVTUiB8IFNfSVdVU1Ip Owo+ICBNT0RVTEVfUEFSTV9ERVNDKG51Y2xlYXJfcGFnZWZsaXAsCj4gIAkJICJGb3JjZSBhdG9t aWMgbW9kZXNldCBmdW5jdGlvbmFsaXR5OyBhc3luY2hyb25vdXMgbW9kZSBpcyBub3QgeWV0IHN1 cHBvcnRlZC4gKGRlZmF1bHQ6IGZhbHNlKS4iKTsKPiAgCj4gIC8qIFdBIHRvIGdldCBhd2F5IHdp dGggdGhlIGRlZmF1bHQgc2V0dGluZyBpbiBWQlQgZm9yIGVhcmx5IHBsYXRmb3Jtcy5XaWxsIGJl IHJlbW92ZWQgKi8KPiAtbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZShlZHBfdnN3aW5nLCBpOTE1 LmVkcF92c3dpbmcsIGludCwgMDQwMCk7Cj4gK21vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoZWRw X3Zzd2luZywgaTkxNS5lZHBfdnN3aW5nLCBpbnQsIFNfSVJVU1IpOwo+ICBNT0RVTEVfUEFSTV9E RVNDKGVkcF92c3dpbmcsCj4gIAkJICJJZ25vcmUvT3ZlcnJpZGUgdnN3aW5nIHByZS1lbXBoIHRh YmxlIHNlbGVjdGlvbiBmcm9tIFZCVCAiCj4gIAkJICIoMD11c2UgdmFsdWUgZnJvbSB2YnQgW2Rl ZmF1bHRdLCAxPWxvdyBwb3dlciBzd2luZygyMDBtViksIgo+ICAJCSAiMj1kZWZhdWx0IHN3aW5n KDQwMG1WKSkiKTsKPiAgCj4gLW1vZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoZW5hYmxlX2d1Y19z dWJtaXNzaW9uLCBpOTE1LmVuYWJsZV9ndWNfc3VibWlzc2lvbiwgYm9vbCwgMDQwMCk7Cj4gK21v ZHVsZV9wYXJhbV9uYW1lZF91bnNhZmUoZW5hYmxlX2d1Y19zdWJtaXNzaW9uLCBpOTE1LmVuYWJs ZV9ndWNfc3VibWlzc2lvbiwgYm9vbCwgU19JUlVTUik7Cj4gIE1PRFVMRV9QQVJNX0RFU0MoZW5h YmxlX2d1Y19zdWJtaXNzaW9uLCAiRW5hYmxlIEd1QyBzdWJtaXNzaW9uIChkZWZhdWx0OmZhbHNl KSIpOwo+ICAKPiAtbW9kdWxlX3BhcmFtX25hbWVkKGd1Y19sb2dfbGV2ZWwsIGk5MTUuZ3VjX2xv Z19sZXZlbCwgaW50LCAwNDAwKTsKPiArbW9kdWxlX3BhcmFtX25hbWVkKGd1Y19sb2dfbGV2ZWws IGk5MTUuZ3VjX2xvZ19sZXZlbCwgaW50LCBTX0lSVVNSKTsKPiAgTU9EVUxFX1BBUk1fREVTQyhn dWNfbG9nX2xldmVsLAo+ICAJIkd1QyBmaXJtd2FyZSBsb2dnaW5nIGxldmVsICgtMTpkaXNhYmxl ZCAoZGVmYXVsdCksIDAtMzplbmFibGVkKSIpOwo+ICAKPiAtbW9kdWxlX3BhcmFtX25hbWVkX3Vu c2FmZShlbmFibGVfZHBfbXN0LCBpOTE1LmVuYWJsZV9kcF9tc3QsIGJvb2wsIDA2MDApOwo+ICtt b2R1bGVfcGFyYW1fbmFtZWRfdW5zYWZlKGVuYWJsZV9kcF9tc3QsIGk5MTUuZW5hYmxlX2RwX21z dCwgYm9vbCwgU19JUlVTUiB8IFNfSVdVU1IpOwo+ICBNT0RVTEVfUEFSTV9ERVNDKGVuYWJsZV9k cF9tc3QsCj4gIAkiRW5hYmxlIG11bHRpLXN0cmVhbSB0cmFuc3BvcnQgKE1TVCkgZm9yIG5ldyBE aXNwbGF5UG9ydCBzaW5rcy4gKGRlZmF1bHQ6IHRydWUpIik7Cj4gLW1vZHVsZV9wYXJhbV9uYW1l ZF91bnNhZmUoaW5qZWN0X2xvYWRfZmFpbHVyZSwgaTkxNS5pbmplY3RfbG9hZF9mYWlsdXJlLCB1 aW50LCAwNDAwKTsKPiArbW9kdWxlX3BhcmFtX25hbWVkX3Vuc2FmZShpbmplY3RfbG9hZF9mYWls dXJlLCBpOTE1LmluamVjdF9sb2FkX2ZhaWx1cmUsIHVpbnQsIFNfSVJVU1IpOwo+ICBNT0RVTEVf UEFSTV9ERVNDKGluamVjdF9sb2FkX2ZhaWx1cmUsCj4gIAkiRm9yY2UgYW4gZXJyb3IgYWZ0ZXIg YSBudW1iZXIgb2YgZmFpbHVyZSBjaGVjayBwb2ludHMgKDA6ZGlzYWJsZWQgKGRlZmF1bHQpLCBO OmZvcmNlIGZhaWx1cmUgYXQgdGhlIE50aCBmYWlsdXJlIGNoZWNrIHBvaW50KSIpOwo+IC0tIAo+ IDIuOS4yCj4gCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KPiBJbnRlbC1nZnggbWFpbGluZyBsaXN0Cj4gSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9w Lm9yZwo+IGh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50 ZWwtZ2Z4CgotLSAKVmlsbGUgU3lyasOkbMOkCkludGVsIE9UQwpfX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1k ZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcv bWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756780AbcHBR6n (ORCPT ); Tue, 2 Aug 2016 13:58:43 -0400 Received: from mga01.intel.com ([192.55.52.88]:56176 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755851AbcHBLis (ORCPT ); Tue, 2 Aug 2016 07:38:48 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,460,1464678000"; d="scan'208";a="743071093" Date: Tue, 2 Aug 2016 14:37:37 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Baole Ni Cc: daniel.vetter@intel.com, jani.nikula@linux.intel.com, airlied@linux.ie, kyungmin.park@samsung.com, kgene@kernel.org, k.kozlowski@samsung.com, dougthompson@xmission.com, bp@alien8.de, wuninsu@gmail.com, chuansheng.liu@intel.com, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, treding@nvidia.com Subject: Re: [Intel-gfx] [PATCH 0197/1285] Replace numeric parameter like 0444 with macro Message-ID: <20160802113737.GT4329@intel.com> References: <20160802104847.26886-1-baolex.ni@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20160802104847.26886-1-baolex.ni@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 02, 2016 at 06:48:47PM +0800, Baole Ni wrote: > I find that the developers often just specified the numeric value > when calling a macro which is defined with a parameter for access permission. > As we know, these numeric value for access permission have had the corresponding macro, > and that using macro can improve the robustness and readability of the code, > thus, I suggest replacing the numeric parameter with the macro. > > Signed-off-by: Chuansheng Liu > Signed-off-by: Baole Ni > --- > drivers/gpu/drm/i915/i915_params.c | 64 +++++++++++++++++++------------------- > 1 file changed, 32 insertions(+), 32 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c > index 1779f02..7184e06 100644 > --- a/drivers/gpu/drm/i915/i915_params.c > +++ b/drivers/gpu/drm/i915/i915_params.c > @@ -60,22 +60,22 @@ struct i915_params i915 __read_mostly = { > .inject_load_failure = 0, > }; > > -module_param_named(modeset, i915.modeset, int, 0400); > +module_param_named(modeset, i915.modeset, int, S_IRUSR); At least I can't read those macros. Octal is much clearer IMO. > MODULE_PARM_DESC(modeset, > "Use kernel modesetting [KMS] (0=disable, " > "1=on, -1=force vga console preference [default])"); > > -module_param_named_unsafe(panel_ignore_lid, i915.panel_ignore_lid, int, 0600); > +module_param_named_unsafe(panel_ignore_lid, i915.panel_ignore_lid, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(panel_ignore_lid, > "Override lid status (0=autodetect, 1=autodetect disabled [default], " > "-1=force lid closed, -2=force lid open)"); > > -module_param_named_unsafe(semaphores, i915.semaphores, int, 0400); > +module_param_named_unsafe(semaphores, i915.semaphores, int, S_IRUSR); > MODULE_PARM_DESC(semaphores, > "Use semaphores for inter-ring sync " > "(default: -1 (use per-chip defaults))"); > > -module_param_named_unsafe(enable_rc6, i915.enable_rc6, int, 0400); > +module_param_named_unsafe(enable_rc6, i915.enable_rc6, int, S_IRUSR); > MODULE_PARM_DESC(enable_rc6, > "Enable power-saving render C-state 6. " > "Different stages can be selected via bitmask values " > @@ -83,82 +83,82 @@ MODULE_PARM_DESC(enable_rc6, > "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " > "default: -1 (use per-chip default)"); > > -module_param_named_unsafe(enable_dc, i915.enable_dc, int, 0400); > +module_param_named_unsafe(enable_dc, i915.enable_dc, int, S_IRUSR); > MODULE_PARM_DESC(enable_dc, > "Enable power-saving display C-states. " > "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)"); > > -module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, 0600); > +module_param_named_unsafe(enable_fbc, i915.enable_fbc, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(enable_fbc, > "Enable frame buffer compression for power savings " > "(default: -1 (use per-chip default))"); > > -module_param_named_unsafe(lvds_channel_mode, i915.lvds_channel_mode, int, 0400); > +module_param_named_unsafe(lvds_channel_mode, i915.lvds_channel_mode, int, S_IRUSR); > MODULE_PARM_DESC(lvds_channel_mode, > "Specify LVDS channel mode " > "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)"); > > -module_param_named_unsafe(lvds_use_ssc, i915.panel_use_ssc, int, 0600); > +module_param_named_unsafe(lvds_use_ssc, i915.panel_use_ssc, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(lvds_use_ssc, > "Use Spread Spectrum Clock with panels [LVDS/eDP] " > "(default: auto from VBT)"); > > -module_param_named_unsafe(vbt_sdvo_panel_type, i915.vbt_sdvo_panel_type, int, 0400); > +module_param_named_unsafe(vbt_sdvo_panel_type, i915.vbt_sdvo_panel_type, int, S_IRUSR); > MODULE_PARM_DESC(vbt_sdvo_panel_type, > "Override/Ignore selection of SDVO panel mode in the VBT " > "(-2=ignore, -1=auto [default], index in VBT BIOS table)"); > > -module_param_named_unsafe(reset, i915.reset, bool, 0600); > +module_param_named_unsafe(reset, i915.reset, bool, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); > > -module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, 0644); > +module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); > MODULE_PARM_DESC(enable_hangcheck, > "Periodically check GPU activity for detecting hangs. " > "WARNING: Disabling this can cause system wide hangs. " > "(default: true)"); > > -module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, 0400); > +module_param_named_unsafe(enable_ppgtt, i915.enable_ppgtt, int, S_IRUSR); > MODULE_PARM_DESC(enable_ppgtt, > "Override PPGTT usage. " > "(-1=auto [default], 0=disabled, 1=aliasing, 2=full, 3=full with extended address space)"); > > -module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, 0400); > +module_param_named_unsafe(enable_execlists, i915.enable_execlists, int, S_IRUSR); > MODULE_PARM_DESC(enable_execlists, > "Override execlists usage. " > "(-1=auto [default], 0=disabled, 1=enabled)"); > > -module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600); > +module_param_named_unsafe(enable_psr, i915.enable_psr, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(enable_psr, "Enable PSR " > "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) " > "Default: -1 (use per-chip default)"); > > -module_param_named_unsafe(preliminary_hw_support, i915.preliminary_hw_support, int, 0400); > +module_param_named_unsafe(preliminary_hw_support, i915.preliminary_hw_support, int, S_IRUSR); > MODULE_PARM_DESC(preliminary_hw_support, > "Enable preliminary hardware support."); > > -module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0400); > +module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, S_IRUSR); > MODULE_PARM_DESC(disable_power_well, > "Disable display power wells when possible " > "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)"); > > -module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600); > +module_param_named_unsafe(enable_ips, i915.enable_ips, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)"); > > -module_param_named(fastboot, i915.fastboot, bool, 0600); > +module_param_named(fastboot, i915.fastboot, bool, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(fastboot, > "Try to skip unnecessary mode sets at boot time (default: false)"); > > -module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, 0600); > +module_param_named_unsafe(prefault_disable, i915.prefault_disable, bool, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(prefault_disable, > "Disable page prefaulting for pread/pwrite/reloc (default:false). " > "For developers only."); > > -module_param_named_unsafe(load_detect_test, i915.load_detect_test, bool, 0600); > +module_param_named_unsafe(load_detect_test, i915.load_detect_test, bool, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(load_detect_test, > "Force-enable the VGA load detect code for testing (default:false). " > "For developers only."); > > -module_param_named_unsafe(invert_brightness, i915.invert_brightness, int, 0600); > +module_param_named_unsafe(invert_brightness, i915.invert_brightness, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(invert_brightness, > "Invert backlight brightness " > "(-1 force normal, 0 machine defaults, 1 force inversion), please " > @@ -166,47 +166,47 @@ MODULE_PARM_DESC(invert_brightness, > "to dri-devel@lists.freedesktop.org, if your machine needs it. " > "It will then be included in an upcoming module version."); > > -module_param_named(disable_display, i915.disable_display, bool, 0400); > +module_param_named(disable_display, i915.disable_display, bool, S_IRUSR); > MODULE_PARM_DESC(disable_display, "Disable display (default: false)"); > > -module_param_named_unsafe(enable_cmd_parser, i915.enable_cmd_parser, int, 0600); > +module_param_named_unsafe(enable_cmd_parser, i915.enable_cmd_parser, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(enable_cmd_parser, > "Enable command parsing (1=enabled [default], 0=disabled)"); > > -module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, 0600); > +module_param_named_unsafe(use_mmio_flip, i915.use_mmio_flip, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(use_mmio_flip, > "use MMIO flips (-1=never, 0=driver discretion [default], 1=always)"); > > -module_param_named(mmio_debug, i915.mmio_debug, int, 0600); > +module_param_named(mmio_debug, i915.mmio_debug, int, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(mmio_debug, > "Enable the MMIO debug code for the first N failures (default: off). " > "This may negatively affect performance."); > > -module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, 0600); > +module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(verbose_state_checks, > "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); > > -module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, 0600); > +module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(nuclear_pageflip, > "Force atomic modeset functionality; asynchronous mode is not yet supported. (default: false)."); > > /* WA to get away with the default setting in VBT for early platforms.Will be removed */ > -module_param_named_unsafe(edp_vswing, i915.edp_vswing, int, 0400); > +module_param_named_unsafe(edp_vswing, i915.edp_vswing, int, S_IRUSR); > MODULE_PARM_DESC(edp_vswing, > "Ignore/Override vswing pre-emph table selection from VBT " > "(0=use value from vbt [default], 1=low power swing(200mV)," > "2=default swing(400mV))"); > > -module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, bool, 0400); > +module_param_named_unsafe(enable_guc_submission, i915.enable_guc_submission, bool, S_IRUSR); > MODULE_PARM_DESC(enable_guc_submission, "Enable GuC submission (default:false)"); > > -module_param_named(guc_log_level, i915.guc_log_level, int, 0400); > +module_param_named(guc_log_level, i915.guc_log_level, int, S_IRUSR); > MODULE_PARM_DESC(guc_log_level, > "GuC firmware logging level (-1:disabled (default), 0-3:enabled)"); > > -module_param_named_unsafe(enable_dp_mst, i915.enable_dp_mst, bool, 0600); > +module_param_named_unsafe(enable_dp_mst, i915.enable_dp_mst, bool, S_IRUSR | S_IWUSR); > MODULE_PARM_DESC(enable_dp_mst, > "Enable multi-stream transport (MST) for new DisplayPort sinks. (default: true)"); > -module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, 0400); > +module_param_named_unsafe(inject_load_failure, i915.inject_load_failure, uint, S_IRUSR); > MODULE_PARM_DESC(inject_load_failure, > "Force an error after a number of failure check points (0:disabled (default), N:force failure at the Nth failure check point)"); > -- > 2.9.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC