From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matt Roper Subject: Re: [PATCH v5 3/6] drm/i915/skl: Update plane watermarks atomically during plane updates Date: Wed, 3 Aug 2016 14:14:53 -0700 Message-ID: <20160803211453.GA871@intel.com> References: <1470163975-30467-1-git-send-email-cpaul@redhat.com> <1470163975-30467-4-git-send-email-cpaul@redhat.com> <20160802212033.GY32025@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20160802212033.GY32025@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Lyude Cc: dri-devel@lists.freedesktop.org, David Airlie , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Hans de Goede , Daniel Vetter List-Id: dri-devel@lists.freedesktop.org T24gVHVlLCBBdWcgMDIsIDIwMTYgYXQgMDI6MjA6MzNQTSAtMDcwMCwgTWF0dCBSb3BlciB3cm90 ZToKPiBPbiBUdWUsIEF1ZyAwMiwgMjAxNiBhdCAwMjo1Mjo1MVBNIC0wNDAwLCBMeXVkZSB3cm90 ZToKPiA+IFRoYW5rcyB0byBWaWxsZSBmb3Igc3VnZ2VzdGluZyB0aGlzIGFzIGEgcG90ZW50aWFs IHNvbHV0aW9uIHRvIHBpcGUKPiA+IHVuZGVycnVucyBvbiBTa3lsYWtlLgo+ID4gCj4gPiBPbiBT a3lsYWtlIGFsbCBvZiB0aGUgcmVnaXN0ZXJzIGZvciBjb25maWd1cmluZyBwbGFuZXMsIGluY2x1 ZGluZyB0aGUKPiA+IHJlZ2lzdGVycyBmb3IgY29uZmlndXJpbmcgdGhlaXIgd2F0ZXJtYXJrcywg YXJlIGRvdWJsZSBidWZmZXJlZC4gTmV3Cj4gPiB2YWx1ZXMgd3JpdHRlbiB0byB0aGVtIHdvbid0 IHRha2UgZWZmZWN0IHVudGlsIHNhaWQgcmVnaXN0ZXJzIGFyZQo+ID4gImFybWVkIiwgd2hpY2gg aXMgZG9uZSBieSB3cml0aW5nIHRvIHRoZSBQTEFORV9TVVJGIChvciBpbiB0aGUgY2FzZSBvZgo+ ID4gY3Vyc29yIHBsYW5lcywgdGhlIENVUkJBU0UgcmVnaXN0ZXIpIHJlZ2lzdGVyLgo+ID4gCj4g PiBXaXRoIHRoaXMgaW4gbWluZCwgdXAgdW50aWwgbm93IHdlJ3ZlIGJlZW4gdXBkYXRpbmcgd2F0 ZXJtYXJrcyBvbiBza2wKPiA+IGxpa2UgdGhpczoKPiA+IAo+ID4gICBub24tbW9kZXNldCB7Cj4g PiAgICAtIGNhbGN1bGF0ZSAoZHVyaW5nIGF0b21pYyBjaGVjayBwaGFzZSkKPiA+ICAgIC0gZmlu aXNoX2F0b21pY19jb21taXQ6Cj4gPiAgICAgIC0gaW50ZWxfcHJlX3BsYW5lX3VwZGF0ZToKPiA+ ICAgICAgICAgLSBpbnRlbF91cGRhdGVfd2F0ZXJtYXJrcygpCj4gPiAgICAgIC0ge3ZibGFuayBo YXBwZW5zOyBuZXcgd2F0ZXJtYXJrcyArIG9sZCBwbGFuZSB2YWx1ZXMgPT4gdW5kZXJydW4gfQo+ ID4gICAgICAtIGRybV9hdG9taWNfaGVscGVyX2NvbW1pdF9wbGFuZXNfb25fY3J0YzoKPiA+ICAg ICAgICAgLSBzdGFydCB2YmxhbmsgZXZhc2lvbgo+ID4gICAgICAgICAtIHdyaXRlIG5ldyBwbGFu ZSByZWdpc3RlcnMKPiA+ICAgICAgICAgLSBlbmQgdmJsYW5rIGV2YXNpb24KPiA+ICAgfQo+ID4g Cj4gPiAgIG9yCj4gPiAKPiA+ICAgbW9kZXNldCB7Cj4gPiAgICAtIGNhbGN1bGF0ZSAoZHVyaW5n IGF0b21pYyBjaGVjayBwaGFzZSkKPiA+ICAgIC0gZmluaXNoX2F0b21pY19jb21taXQ6Cj4gPiAg ICAgIC0gY3J0Y19lbmFibGU6Cj4gPiAgICAgICAgIC0gaW50ZWxfdXBkYXRlX3dhdGVybWFya3Mo KQo+ID4gICAgICAtIHt2YmxhbmsgaGFwcGVuczsgbmV3IHdhdGVybWFya3MgKyBvbGQgcGxhbmUg dmFsdWVzID0+IHVuZGVycnVuIH0KPiA+ICAgICAgLSBkcm1fYXRvbWljX2hlbHBlcl9jb21taXRf cGxhbmVzX29uX2NydGM6Cj4gPiAgICAgICAgIC0gc3RhcnQgdmJsYW5rIGV2YXNpb24KPiA+ICAg ICAgICAgLSB3cml0ZSBuZXcgcGxhbmUgcmVnaXN0ZXJzCj4gPiAgICAgICAgIC0gZW5kIHZibGFu ayBldmFzaW9uCj4gPiAgIH0KPiA+IAo+ID4gTm93IHdlIHVwZGF0ZSB3YXRlcm1hcmtzIGF0b21p Y2FsbHkgbGlrZSB0aGlzOgo+ID4gCj4gPiAgIG5vbi1tb2Rlc2V0IHsKPiA+ICAgIC0gY2FsY3Vs YXRlIChkdXJpbmcgYXRvbWljIGNoZWNrIHBoYXNlKQo+ID4gICAgLSBmaW5pc2hfYXRvbWljX2Nv bW1pdDoKPiA+ICAgICAgLSBpbnRlbF9wcmVfcGxhbmVfdXBkYXRlOgo+ID4gICAgICAgICAtIGlu dGVsX3VwZGF0ZV93YXRlcm1hcmtzKCkgKHdtIHZhbHVlcyBhcmVuJ3Qgd3JpdHRlbiB5ZXQpCj4g PiAgICAgIC0gZHJtX2F0b21pY19oZWxwZXJfY29tbWl0X3BsYW5lc19vbl9jcnRjOgo+ID4gICAg ICAgICAtIHN0YXJ0IHZibGFuayBldmFzaW9uCj4gPiAgICAgICAgIC0gd3JpdGUgbmV3IHBsYW5l IHJlZ2lzdGVycwo+ID4gICAgICAgICAtIHdyaXRlIG5ldyB3bSB2YWx1ZXMKPiA+ICAgICAgICAg LSBlbmQgdmJsYW5rIGV2YXNpb24KPiA+ICAgfQo+ID4gCj4gPiAgIG1vZGVzZXQgewo+ID4gICAg LSBjYWxjdWxhdGUgKGR1cmluZyBhdG9taWMgY2hlY2sgcGhhc2UpCj4gPiAgICAtIGZpbmlzaF9h dG9taWNfY29tbWl0Ogo+ID4gICAgICAtIGNydGNfZW5hYmxlOgo+ID4gICAgICAgICAtIGludGVs X3VwZGF0ZV93YXRlcm1hcmtzKCkgKGFjdHVhbCB3bSB2YWx1ZXMgYXJlbid0IHdyaXR0ZW4KPiA+ ICAgICAgICAgICB5ZXQpCj4gPiAgICAgIC0gZHJtX2F0b21pY19oZWxwZXJfY29tbWl0X3BsYW5l c19vbl9jcnRjOgo+ID4gICAgICAgICAtIHN0YXJ0IHZibGFuayBldmFzaW9uCj4gPiAgICAgICAg IC0gd3JpdGUgbmV3IHBsYW5lIHJlZ2lzdGVycwo+ID4gCS0gd3JpdGUgbmV3IHdtIHZhbHVlcwo+ ID4gICAgICAgICAtIGVuZCB2YmxhbmsgZXZhc2lvbgo+ID4gICB9Cj4gPiAKPiA+IFNvIHRoaXMg cGF0Y2ggbW92ZXMgYWxsIG9mIHRoZSB3YXRlcm1hcmsgd3JpdGVzIGludG8gdGhlIHJpZ2h0IHBs YWNlOwo+ID4gaW5zaWRlIG9mIHRoZSB2YmxhbmsgZXZhc2lvbiB3aGVyZSB3ZSB1cGRhdGUgYWxs IG9mIHRoZSByZWdpc3RlcnMgZm9yCj4gPiBlYWNoIHBsYW5lLiBXaGlsZSB0aGlzIHBhdGNoIGRv ZXNuJ3QgZml4IGV2ZXJ5dGhpbmcsIGl0IGRvZXMgYWxsb3cgdXMgdG8KPiA+IHVwZGF0ZSB0aGUg d2F0ZXJtYXJrIHZhbHVlcyBpbiB0aGUgd2F5IHRoZSBoYXJkd2FyZSBleHBlY3RzIHVzIHRvLgo+ ID4gCj4gPiBDaGFuZ2VzIHNpbmNlIG9yaWdpbmFsIHBhdGNoIHNlcmllczoKPiA+ICAtIFJlbW92 ZSBtdXRleF9sb2NrL211dGV4X3VubG9jayBzaW5jZSB0aGV5IGRvbid0IGRvIGFueXRoaW5nIGFu ZCB3ZSdyZQo+ID4gICAgbm90IHRvdWNoaW5nIGdsb2JhbCBzdGF0ZQo+ID4gIC0gTW92ZSBza2xf d3JpdGVfY3Vyc29yX3dtL3NrbF93cml0ZV9wbGFuZV93bSBmdW5jdGlvbnMgaW50bwo+ID4gICAg aW50ZWxfcG0uYywgbWFrZSBleHRlcm5hbGx5IHZpc2libGUKPiA+ICAtIEFkZCBza2xfd3JpdGVf cGxhbmVfd20gY2FsbHMgdG8gc2tsX3VwZGF0ZV9wbGFuZQo+ID4gIC0gRml4IGNvbmRpdGlvbmFs IGZvciBmb3IgbG9vcCBpbiBza2xfd3JpdGVfcGxhbmVfd20gKGxldmVsIDwgbWF4X2xldmVsCj4g PiAgICBzaG91bGQgYmUgbGV2ZWwgPD0gbWF4X2xldmVsKQo+ID4gIC0gTWFrZSBkaWFncmFtIGlu IGNvbW1pdCBtb3JlIGFjY3VyYXRlIHRvIHdoYXQncyBhY3R1YWxseSBoYXBwZW5pbmcKPiA+ICAt IEFkZCBGaXhlczoKPiA+IAo+ID4gQ2hhbmdlcyBzaW5jZSB2MToKPiA+ICAtIFVzZSBJU19HRU45 KCkgaW5zdGVhZCBvZiBJU19TS1lMQUtFKCkgc2luY2UgdGhlc2UgZml4ZXMgYXBwbHkgdG8gbW9y ZQo+ID4gICAgdGhlbiBqdXN0IFNreWxha2UKPiA+ICAtIFVwZGF0ZSBkZXNjcmlwdGlvbiB0byBt YWtlIGl0IGNsZWFyIHRoaXMgcGF0Y2ggZG9lc24ndCBmaXggZXZlcnl0aGluZwo+ID4gIC0gQ2hl Y2sgaWYgcGlwZXMgd2VyZSBhY3R1YWxseSBjaGFuZ2VkIGJlZm9yZSB3cml0aW5nIHdhdGVybWFy a3MKPiA+IAo+ID4gQ2hhbmdlcyBzaW5jZSB2MjoKPiA+ICAtIFdyaXRlIFBJUEVfV01fTElORVRJ TUUgZHVyaW5nIHZibGFuayBldmFzaW9uCj4gPiAKPiA+IENoYW5nZXMgc2luY2UgdjM6Cj4gPiAg LSBSZWJhc2UgYWdhaW5zdCBuZXcgU0FHViBwYXRjaCBjaGFuZ2VzCj4gPiAKPiA+IENoYW5nZXMg c2luY2UgdjQ6Cj4gPiAgLSBBZGQgYSBwYXJhbWV0ZXIgdG8gY2hvb3NlIHdoYXQgc2tsX3dtX3Zh bHVlcyBzdHJ1Y3QgdG8gdXNlIHdoZW4KPiA+ICAgIHdyaXRpbmcgbmV3IHBsYW5lIHdhdGVybWFy a3MKPiA+IAo+ID4gRml4ZXM6IDJkNDFjMGI1OWFmYyAoImRybS9pOTE1L3NrbDogU0tMIFdhdGVy bWFyayBDb21wdXRhdGlvbiIpCj4gPiBTaWduZWQtb2ZmLWJ5OiBMeXVkZSA8Y3BhdWxAcmVkaGF0 LmNvbT4KPiA+IENjOiBzdGFibGVAdmdlci5rZXJuZWwub3JnCj4gPiBDYzogVmlsbGUgU3lyasOk bMOkIDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPiA+IENjOiBEYW5pZWwgVmV0dGVy IDxkYW5pZWwudmV0dGVyQGludGVsLmNvbT4KPiA+IENjOiBSYWRoYWtyaXNobmEgU3JpcGFkYSA8 cmFkaGFrcmlzaG5hLnNyaXBhZGFAaW50ZWwuY29tPgo+ID4gQ2M6IEhhbnMgZGUgR29lZGUgPGhk ZWdvZWRlQHJlZGhhdC5jb20+Cj4gPiBDYzogTWF0dCBSb3BlciA8bWF0dGhldy5kLnJvcGVyQGlu dGVsLmNvbT4KCkkgaW1hZ2luZSB3ZSdsbCBldmVudHVhbGx5IHByb2JhYmx5IHdhbnQgdG8gY3Jl YXRlIGEgbmV3IGRpc3BsYXkgdmZ1bmMKdG8gaGFuZGxlIHBsYXRmb3JtLXNwZWNpZmljIHBpcGUt bGV2ZWwgc3R1ZmYgdGhhdCBuZWVkcyB0byBoYXBwZW4gdW5kZXIKdmJsYW5rIGV2YXNpb24gKGxp a2UgdGhlIHNjYWxlcnMgYW5kIGxpbmV0aW1lIFdNIHdlIGhhdmUgdG9kYXkpIHRvIGtlZXAKdGhl IGNvZGUgY2xlYW47IG1heWJlIGFkZCBhIFRPRE8gY29tbWVudCB0byB0aGF0IGVmZmVjdD8KCkFu eXdheSwgdGhpcyBsb29rcyBnb29kIGVub3VnaCBmb3Igbm93LCBzbwoKUmV2aWV3ZWQtYnk6IE1h dHQgUm9wZXIgPG1hdHRoZXcuZC5yb3BlckBpbnRlbC5jb20+Cgo+ID4gLS0tCj4gPiAgZHJpdmVy cy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jIHwgIDggKysrKysKPiA+ICBkcml2ZXJzL2dw dS9kcm0vaTkxNS9pbnRlbF9kcnYuaCAgICAgfCAgNSArKysrCj4gPiAgZHJpdmVycy9ncHUvZHJt L2k5MTUvaW50ZWxfcG0uYyAgICAgIHwgNTggKysrKysrKysrKysrKysrKysrKysrKysrKystLS0t LS0tLS0tCj4gPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfc3ByaXRlLmMgIHwgIDYgKysr Kwo+ID4gIDQgZmlsZXMgY2hhbmdlZCwgNjEgaW5zZXJ0aW9ucygrKSwgMTYgZGVsZXRpb25zKC0p Cj4gPiAKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kaXNwbGF5 LmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kaXNwbGF5LmMKPiA+IGluZGV4IDc2YmE3 OWYuLjc5ZDE0NmMgMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9k aXNwbGF5LmMKPiA+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYwo+ ID4gQEAgLTI5ODAsNiArMjk4MCw3IEBAIHN0YXRpYyB2b2lkIHNreWxha2VfdXBkYXRlX3ByaW1h cnlfcGxhbmUoc3RydWN0IGRybV9wbGFuZSAqcGxhbmUsCj4gPiAgCXN0cnVjdCBpbnRlbF9jcnRj ICppbnRlbF9jcnRjID0gdG9faW50ZWxfY3J0YyhjcnRjX3N0YXRlLT5iYXNlLmNydGMpOwo+ID4g IAlzdHJ1Y3QgZHJtX2ZyYW1lYnVmZmVyICpmYiA9IHBsYW5lX3N0YXRlLT5iYXNlLmZiOwo+ID4g IAlzdHJ1Y3QgZHJtX2k5MTVfZ2VtX29iamVjdCAqb2JqID0gaW50ZWxfZmJfb2JqKGZiKTsKPiA+ ICsJc3RydWN0IHNrbF93bV92YWx1ZXMgKndtID0gJmRldl9wcml2LT53bS5za2xfcmVzdWx0czsK PiA+ICAJaW50IHBpcGUgPSBpbnRlbF9jcnRjLT5waXBlOwo+ID4gIAl1MzIgcGxhbmVfY3RsLCBz dHJpZGVfZGl2LCBzdHJpZGU7Cj4gPiAgCXUzMiB0aWxlX2hlaWdodCwgcGxhbmVfb2Zmc2V0LCBw bGFuZV9zaXplOwo+ID4gQEAgLTMwMzEsNiArMzAzMiw5IEBAIHN0YXRpYyB2b2lkIHNreWxha2Vf dXBkYXRlX3ByaW1hcnlfcGxhbmUoc3RydWN0IGRybV9wbGFuZSAqcGxhbmUsCj4gPiAgCWludGVs X2NydGMtPmFkanVzdGVkX3ggPSB4X29mZnNldDsKPiA+ICAJaW50ZWxfY3J0Yy0+YWRqdXN0ZWRf eSA9IHlfb2Zmc2V0Owo+ID4gIAo+ID4gKwlpZiAod20tPmRpcnR5X3BpcGVzICYgZHJtX2NydGNf bWFzaygmaW50ZWxfY3J0Yy0+YmFzZSkpCj4gPiArCSAgICBza2xfd3JpdGVfcGxhbmVfd20oaW50 ZWxfY3J0Yywgd20sIDApOwo+ID4gKwo+ID4gIAlJOTE1X1dSSVRFKFBMQU5FX0NUTChwaXBlLCAw KSwgcGxhbmVfY3RsKTsKPiA+ICAJSTkxNV9XUklURShQTEFORV9PRkZTRVQocGlwZSwgMCksIHBs YW5lX29mZnNldCk7Cj4gPiAgCUk5MTVfV1JJVEUoUExBTkVfU0laRShwaXBlLCAwKSwgcGxhbmVf c2l6ZSk7Cj4gPiBAQCAtMTAyNDMsOSArMTAyNDcsMTMgQEAgc3RhdGljIHZvaWQgaTl4eF91cGRh dGVfY3Vyc29yKHN0cnVjdCBkcm1fY3J0YyAqY3J0YywgdTMyIGJhc2UsCj4gPiAgCXN0cnVjdCBk cm1fZGV2aWNlICpkZXYgPSBjcnRjLT5kZXY7Cj4gPiAgCXN0cnVjdCBkcm1faTkxNV9wcml2YXRl ICpkZXZfcHJpdiA9IHRvX2k5MTUoZGV2KTsKPiA+ICAJc3RydWN0IGludGVsX2NydGMgKmludGVs X2NydGMgPSB0b19pbnRlbF9jcnRjKGNydGMpOwo+ID4gKwlzdHJ1Y3Qgc2tsX3dtX3ZhbHVlcyAq d20gPSAmZGV2X3ByaXYtPndtLnNrbF9yZXN1bHRzOwo+ID4gIAlpbnQgcGlwZSA9IGludGVsX2Ny dGMtPnBpcGU7Cj4gPiAgCXVpbnQzMl90IGNudGwgPSAwOwo+ID4gIAo+ID4gKwlpZiAoSVNfR0VO OShkZXZfcHJpdikgJiYgd20tPmRpcnR5X3BpcGVzICYgZHJtX2NydGNfbWFzayhjcnRjKSkKPiA+ ICsJCXNrbF93cml0ZV9jdXJzb3Jfd20oaW50ZWxfY3J0Yywgd20pOwo+ID4gKwo+ID4gIAlpZiAo cGxhbmVfc3RhdGUgJiYgcGxhbmVfc3RhdGUtPnZpc2libGUpIHsKPiA+ICAJCWNudGwgPSBNQ1VS U09SX0dBTU1BX0VOQUJMRTsKPiA+ICAJCXN3aXRjaCAocGxhbmVfc3RhdGUtPmJhc2UuY3J0Y193 KSB7Cj4gPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHJ2LmggYi9k cml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ID4gaW5kZXggNmIwNTMyYS4uMWI0NDRk MyAxMDA2NDQKPiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rydi5oCj4gPiAr KysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ID4gQEAgLTE3MTEsNiArMTcx MSwxMSBAQCB2b2lkIHNrbF9kZGJfZ2V0X2h3X3N0YXRlKHN0cnVjdCBkcm1faTkxNV9wcml2YXRl ICpkZXZfcHJpdiwKPiA+ICAJCQkgIHN0cnVjdCBza2xfZGRiX2FsbG9jYXRpb24gKmRkYiAvKiBv dXQgKi8pOwo+ID4gIGludCBza2xfZW5hYmxlX3NhZ3Yoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUg KmRldl9wcml2KTsKPiA+ICBpbnQgc2tsX2Rpc2FibGVfc2FndihzdHJ1Y3QgZHJtX2k5MTVfcHJp dmF0ZSAqZGV2X3ByaXYpOwo+ID4gK3ZvaWQgc2tsX3dyaXRlX2N1cnNvcl93bShzdHJ1Y3QgaW50 ZWxfY3J0YyAqaW50ZWxfY3J0YywKPiA+ICsJCQkgY29uc3Qgc3RydWN0IHNrbF93bV92YWx1ZXMg KndtKTsKPiA+ICt2b2lkIHNrbF93cml0ZV9wbGFuZV93bShzdHJ1Y3QgaW50ZWxfY3J0YyAqaW50 ZWxfY3J0YywKPiA+ICsJCQljb25zdCBzdHJ1Y3Qgc2tsX3dtX3ZhbHVlcyAqd20sCj4gPiArCQkJ aW50IHBsYW5lKTsKPiA+ICB1aW50MzJfdCBpbGtfcGlwZV9waXhlbF9yYXRlKGNvbnN0IHN0cnVj dCBpbnRlbF9jcnRjX3N0YXRlICpwaXBlX2NvbmZpZyk7Cj4gPiAgYm9vbCBpbGtfZGlzYWJsZV9s cF93bShzdHJ1Y3QgZHJtX2RldmljZSAqZGV2KTsKPiA+ICBpbnQgc2FuaXRpemVfcmM2X29wdGlv bihzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsIGludCBlbmFibGVfcmM2KTsKPiA+ IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9wbS5jIGIvZHJpdmVycy9n cHUvZHJtL2k5MTUvaW50ZWxfcG0uYwo+ID4gaW5kZXggN2ZkMjk5ZS4uNTNhZGNiZiAxMDA2NDQK PiA+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKPiA+ICsrKyBiL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKPiA+IEBAIC0zNzk4LDYgKzM3OTgsNDcgQEAgc3Rh dGljIHZvaWQgc2tsX2RkYl9lbnRyeV93cml0ZShzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2 X3ByaXYsCj4gPiAgCQlJOTE1X1dSSVRFKHJlZywgMCk7Cj4gPiAgfQo+ID4gIAo+ID4gK3ZvaWQg c2tsX3dyaXRlX3BsYW5lX3dtKHN0cnVjdCBpbnRlbF9jcnRjICppbnRlbF9jcnRjLAo+ID4gKwkJ CWNvbnN0IHN0cnVjdCBza2xfd21fdmFsdWVzICp3bSwKPiA+ICsJCQlpbnQgcGxhbmUpCj4gPiAr ewo+ID4gKwlzdHJ1Y3QgZHJtX2NydGMgKmNydGMgPSAmaW50ZWxfY3J0Yy0+YmFzZTsKPiA+ICsJ c3RydWN0IGRybV9kZXZpY2UgKmRldiA9IGNydGMtPmRldjsKPiA+ICsJc3RydWN0IGRybV9pOTE1 X3ByaXZhdGUgKmRldl9wcml2ID0gdG9faTkxNShkZXYpOwo+ID4gKwlpbnQgbGV2ZWwsIG1heF9s ZXZlbCA9IGlsa193bV9tYXhfbGV2ZWwoZGV2KTsKPiA+ICsJZW51bSBwaXBlIHBpcGUgPSBpbnRl bF9jcnRjLT5waXBlOwo+ID4gKwo+ID4gKwlpZiAoISh3bS0+ZGlydHlfcGlwZXMgJiBkcm1fY3J0 Y19tYXNrKGNydGMpKSkKPiA+ICsJCXJldHVybjsKPiA+ICsKPiA+ICsJSTkxNV9XUklURShQSVBF X1dNX0xJTkVUSU1FKHBpcGUpLCB3bS0+d21fbGluZXRpbWVbcGlwZV0pOwo+IAo+IEkgdGhpbmsg SSBtZW50aW9uZWQgdGhpcyBvbiB0aGUgcHJldmlvdXMgdmVyc2lvbiwgYnV0IGlmIHdlIHByb2dy YW0gdGhpcwo+IGhlcmUgdGhlbiBpdCBvbmx5IGdldHMgcHJvZ3JhbW1lZCB3aGVuIGEgcGxhbmUg aXMgYmVpbmcgdXBkYXRlZC4gIEl0J3MKPiBwb3NzaWJsZSB0aGF0IHdlIGNvdWxkIGhhdmUgdGhl IGxpbmV0aW1lIHZhbHVlIGNoYW5nZSBkdWUgdG8gYSBzY2FsZXIKPiB1cGRhdGUgb3IgYSBtb2Rl c2V0LCBidXQgd2l0aG91dCBjb3JyZXNwb25kaW5nIHBsYW5lIHVwZGF0ZXMgKGUuZy4sCj4gbWF5 YmUgYWxsIHBsYW5lcyBhcmUgb2ZmKS4gIFNvIHdlIHByb2JhYmx5IG5lZWQgdG8gbWFrZSBzdXJl IHRoaXMgdmFsdWUKPiBnZXRzIHdyaXR0ZW4gb3V0c2lkZSB0aGUgcGxhbmUgdXBkYXRlcyAoYnV0 IHN0aWxsIHVuZGVyIHZibGFuayBldmFzaW9uKS4KPiAKPiA+ICsKPiA+ICsJZm9yIChsZXZlbCA9 IDA7IGxldmVsIDw9IG1heF9sZXZlbDsgbGV2ZWwrKykgewo+ID4gKwkJSTkxNV9XUklURShQTEFO RV9XTShwaXBlLCBwbGFuZSwgbGV2ZWwpLAo+ID4gKwkJCSAgIHdtLT5wbGFuZVtwaXBlXVtwbGFu ZV1bbGV2ZWxdKTsKPiA+ICsJfQo+ID4gKwlJOTE1X1dSSVRFKFBMQU5FX1dNX1RSQU5TKHBpcGUs IHBsYW5lKSwgd20tPnBsYW5lX3RyYW5zW3BpcGVdW3BsYW5lXSk7Cj4gCj4gSSBub3RpY2UgdGhh dCB5b3UgbW92ZWQgdGhlIEREQiB1cGRhdGUgaW50byBza2xfd3JpdGVfY3Vyc29yX3dtKCkgZG93 bgo+IGJlbG93LCBidXQgZGlkbid0IG1vdmUgdGhlIHBsYW5lIEREQiB1cGRhdGUgaW4gaGVyZS4g IEkgcmVhbGl6ZSB5b3UKPiByZW1lZHkgdGhhdCBpbiBwYXRjaCAjNiB3aGVyZSB5b3UgZmluYWxs eSBmaXggdXAgdGhlIGZsdXNoaW5nIG9yZGVyLCBidXQKPiB0aGUgaW5jb25zaXN0ZW5jeSBiZXR3 ZWVuIGhvdyBjdXJzb3IgdnMgIWN1cnNvciBwbGFuZXMgYXJlIGhhbmRsZWQgc2VlbXMKPiBjb25m dXNpbmcuICBDYW4gd2UgZWl0aGVyIG1vdmUgdGhlIHBsYW5lIEREQiB1cGRhdGUgaGVyZSBpbiB0 aGlzIHBhdGNoCj4gKHdlIGRvbid0IGZsdXNoIHByb3Blcmx5IHlldCwgYnV0IHdlJ3JlIHJlYWxs eSBubyB3b3JzZSBvZmYgdGhhbiB3ZQo+IGFscmVhZHkgYXJlKSwgb3IgY2FuIHdlIGRlZmVyIHRo ZSBtb3ZlIG9mIHRoZSBjdXJzb3IgRERCIHRvIHBhdGNoIDYgdG8KPiBrZWVwIHRoZW0gY29uc2lz dGVudD8KPiAKPiAKPiBNYXR0Cj4gCj4gPiArfQo+ID4gKwo+ID4gK3ZvaWQgc2tsX3dyaXRlX2N1 cnNvcl93bShzdHJ1Y3QgaW50ZWxfY3J0YyAqaW50ZWxfY3J0YywKPiA+ICsJCQkgY29uc3Qgc3Ry dWN0IHNrbF93bV92YWx1ZXMgKndtKQo+ID4gK3sKPiA+ICsJc3RydWN0IGRybV9jcnRjICpjcnRj ID0gJmludGVsX2NydGMtPmJhc2U7Cj4gPiArCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBjcnRj LT5kZXY7Cj4gPiArCXN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiA9IHRvX2k5MTUo ZGV2KTsKPiA+ICsJaW50IGxldmVsLCBtYXhfbGV2ZWwgPSBpbGtfd21fbWF4X2xldmVsKGRldik7 Cj4gPiArCWVudW0gcGlwZSBwaXBlID0gaW50ZWxfY3J0Yy0+cGlwZTsKPiA+ICsKPiA+ICsJZm9y IChsZXZlbCA9IDA7IGxldmVsIDw9IG1heF9sZXZlbDsgbGV2ZWwrKykgewo+ID4gKwkJSTkxNV9X UklURShDVVJfV00ocGlwZSwgbGV2ZWwpLAo+ID4gKwkJCSAgIHdtLT5wbGFuZVtwaXBlXVtQTEFO RV9DVVJTT1JdW2xldmVsXSk7Cj4gPiArCX0KPiA+ICsJSTkxNV9XUklURShDVVJfV01fVFJBTlMo cGlwZSksIHdtLT5wbGFuZV90cmFuc1twaXBlXVtQTEFORV9DVVJTT1JdKTsKPiA+ICsKPiA+ICsJ c2tsX2RkYl9lbnRyeV93cml0ZShkZXZfcHJpdiwgQ1VSX0JVRl9DRkcocGlwZSksCj4gPiArCQkJ ICAgICZ3bS0+ZGRiLnBsYW5lW3BpcGVdW1BMQU5FX0NVUlNPUl0pOwo+ID4gK30KPiA+ICsKPiA+ ICBzdGF0aWMgdm9pZCBza2xfd3JpdGVfd21fdmFsdWVzKHN0cnVjdCBkcm1faTkxNV9wcml2YXRl ICpkZXZfcHJpdiwKPiA+ICAJCQkJY29uc3Qgc3RydWN0IHNrbF93bV92YWx1ZXMgKm5ldykKPiA+ ICB7Cj4gPiBAQCAtMzgwNSw3ICszODQ2LDcgQEAgc3RhdGljIHZvaWQgc2tsX3dyaXRlX3dtX3Zh bHVlcyhzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsCj4gPiAgCXN0cnVjdCBpbnRl bF9jcnRjICpjcnRjOwo+ID4gIAo+ID4gIAlmb3JfZWFjaF9pbnRlbF9jcnRjKGRldiwgY3J0Yykg ewo+ID4gLQkJaW50IGksIGxldmVsLCBtYXhfbGV2ZWwgPSBpbGtfd21fbWF4X2xldmVsKGRldik7 Cj4gPiArCQlpbnQgaTsKPiA+ICAJCWVudW0gcGlwZSBwaXBlID0gY3J0Yy0+cGlwZTsKPiA+ICAK PiA+ICAJCWlmICgobmV3LT5kaXJ0eV9waXBlcyAmIGRybV9jcnRjX21hc2soJmNydGMtPmJhc2Up KSA9PSAwKQo+ID4gQEAgLTM4MTMsMjEgKzM4NTQsNiBAQCBzdGF0aWMgdm9pZCBza2xfd3JpdGVf d21fdmFsdWVzKHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwKPiA+ICAJCWlmICgh Y3J0Yy0+YWN0aXZlKQo+ID4gIAkJCWNvbnRpbnVlOwo+ID4gIAo+ID4gLQkJSTkxNV9XUklURShQ SVBFX1dNX0xJTkVUSU1FKHBpcGUpLCBuZXctPndtX2xpbmV0aW1lW3BpcGVdKTsKPiA+IC0KPiA+ IC0JCWZvciAobGV2ZWwgPSAwOyBsZXZlbCA8PSBtYXhfbGV2ZWw7IGxldmVsKyspIHsKPiA+IC0J CQlmb3IgKGkgPSAwOyBpIDwgaW50ZWxfbnVtX3BsYW5lcyhjcnRjKTsgaSsrKQo+ID4gLQkJCQlJ OTE1X1dSSVRFKFBMQU5FX1dNKHBpcGUsIGksIGxldmVsKSwKPiA+IC0JCQkJCSAgIG5ldy0+cGxh bmVbcGlwZV1baV1bbGV2ZWxdKTsKPiA+IC0JCQlJOTE1X1dSSVRFKENVUl9XTShwaXBlLCBsZXZl bCksCj4gPiAtCQkJCSAgIG5ldy0+cGxhbmVbcGlwZV1bUExBTkVfQ1VSU09SXVtsZXZlbF0pOwo+ ID4gLQkJfQo+ID4gLQkJZm9yIChpID0gMDsgaSA8IGludGVsX251bV9wbGFuZXMoY3J0Yyk7IGkr KykKPiA+IC0JCQlJOTE1X1dSSVRFKFBMQU5FX1dNX1RSQU5TKHBpcGUsIGkpLAo+ID4gLQkJCQkg ICBuZXctPnBsYW5lX3RyYW5zW3BpcGVdW2ldKTsKPiA+IC0JCUk5MTVfV1JJVEUoQ1VSX1dNX1RS QU5TKHBpcGUpLAo+ID4gLQkJCSAgIG5ldy0+cGxhbmVfdHJhbnNbcGlwZV1bUExBTkVfQ1VSU09S XSk7Cj4gPiAtCj4gPiAgCQlmb3IgKGkgPSAwOyBpIDwgaW50ZWxfbnVtX3BsYW5lcyhjcnRjKTsg aSsrKSB7Cj4gPiAgCQkJc2tsX2RkYl9lbnRyeV93cml0ZShkZXZfcHJpdiwKPiA+ICAJCQkJCSAg ICBQTEFORV9CVUZfQ0ZHKHBpcGUsIGkpLAo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2ludGVsX3Nwcml0ZS5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfc3ByaXRl LmMKPiA+IGluZGV4IDBkZTkzNWEuLjU1ZDE3M2YgMTAwNjQ0Cj4gPiAtLS0gYS9kcml2ZXJzL2dw dS9kcm0vaTkxNS9pbnRlbF9zcHJpdGUuYwo+ID4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUv aW50ZWxfc3ByaXRlLmMKPiA+IEBAIC0yMDMsNiArMjAzLDkgQEAgc2tsX3VwZGF0ZV9wbGFuZShz dHJ1Y3QgZHJtX3BsYW5lICpkcm1fcGxhbmUsCj4gPiAgCXN0cnVjdCBpbnRlbF9wbGFuZSAqaW50 ZWxfcGxhbmUgPSB0b19pbnRlbF9wbGFuZShkcm1fcGxhbmUpOwo+ID4gIAlzdHJ1Y3QgZHJtX2Zy YW1lYnVmZmVyICpmYiA9IHBsYW5lX3N0YXRlLT5iYXNlLmZiOwo+ID4gIAlzdHJ1Y3QgZHJtX2k5 MTVfZ2VtX29iamVjdCAqb2JqID0gaW50ZWxfZmJfb2JqKGZiKTsKPiA+ICsJc3RydWN0IHNrbF93 bV92YWx1ZXMgKndtID0gJmRldl9wcml2LT53bS5za2xfcmVzdWx0czsKPiA+ICsJc3RydWN0IGRy bV9jcnRjICpjcnRjID0gY3J0Y19zdGF0ZS0+YmFzZS5jcnRjOwo+ID4gKwlzdHJ1Y3QgaW50ZWxf Y3J0YyAqaW50ZWxfY3J0YyA9IHRvX2ludGVsX2NydGMoY3J0Yyk7Cj4gPiAgCWNvbnN0IGludCBw aXBlID0gaW50ZWxfcGxhbmUtPnBpcGU7Cj4gPiAgCWNvbnN0IGludCBwbGFuZSA9IGludGVsX3Bs YW5lLT5wbGFuZSArIDE7Cj4gPiAgCXUzMiBwbGFuZV9jdGwsIHN0cmlkZV9kaXYsIHN0cmlkZTsK PiA+IEBAIC0yMzgsNiArMjQxLDkgQEAgc2tsX3VwZGF0ZV9wbGFuZShzdHJ1Y3QgZHJtX3BsYW5l ICpkcm1fcGxhbmUsCj4gPiAgCWNydGNfdy0tOwo+ID4gIAljcnRjX2gtLTsKPiA+ICAKPiA+ICsJ aWYgKHdtLT5kaXJ0eV9waXBlcyAmIGRybV9jcnRjX21hc2soY3J0YykpCj4gPiArCSAgICBza2xf d3JpdGVfcGxhbmVfd20oaW50ZWxfY3J0Yywgd20sIHBsYW5lKTsKPiA+ICsKPiA+ICAJaWYgKGtl eS0+ZmxhZ3MpIHsKPiA+ICAJCUk5MTVfV1JJVEUoUExBTkVfS0VZVkFMKHBpcGUsIHBsYW5lKSwg a2V5LT5taW5fdmFsdWUpOwo+ID4gIAkJSTkxNV9XUklURShQTEFORV9LRVlNQVgocGlwZSwgcGxh bmUpLCBrZXktPm1heF92YWx1ZSk7Cj4gPiAtLSAKPiA+IDIuNy40Cj4gPiAKPiAKPiAtLSAKPiBN YXR0IFJvcGVyCj4gR3JhcGhpY3MgU29mdHdhcmUgRW5naW5lZXIKPiBJb1RHIFBsYXRmb3JtIEVu YWJsaW5nICYgRGV2ZWxvcG1lbnQKPiBJbnRlbCBDb3Jwb3JhdGlvbgo+ICg5MTYpIDM1Ni0yNzk1 CgotLSAKTWF0dCBSb3BlcgpHcmFwaGljcyBTb2Z0d2FyZSBFbmdpbmVlcgpJb1RHIFBsYXRmb3Jt IEVuYWJsaW5nICYgRGV2ZWxvcG1lbnQKSW50ZWwgQ29ycG9yYXRpb24KKDkxNikgMzU2LTI3OTUK X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758394AbcHCVPx (ORCPT ); Wed, 3 Aug 2016 17:15:53 -0400 Received: from mga02.intel.com ([134.134.136.20]:3155 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756802AbcHCVPt (ORCPT ); Wed, 3 Aug 2016 17:15:49 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,467,1464678000"; d="scan'208";a="1034600594" Date: Wed, 3 Aug 2016 14:14:53 -0700 From: Matt Roper To: Lyude Cc: intel-gfx@lists.freedesktop.org, Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Maarten Lankhorst , stable@vger.kernel.org, Daniel Vetter , Radhakrishna Sripada , Hans de Goede , Jani Nikula , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 3/6] drm/i915/skl: Update plane watermarks atomically during plane updates Message-ID: <20160803211453.GA871@intel.com> References: <1470163975-30467-1-git-send-email-cpaul@redhat.com> <1470163975-30467-4-git-send-email-cpaul@redhat.com> <20160802212033.GY32025@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20160802212033.GY32025@intel.com> User-Agent: Mutt/1.5.20 (2009-06-14) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 02, 2016 at 02:20:33PM -0700, Matt Roper wrote: > On Tue, Aug 02, 2016 at 02:52:51PM -0400, Lyude wrote: > > Thanks to Ville for suggesting this as a potential solution to pipe > > underruns on Skylake. > > > > On Skylake all of the registers for configuring planes, including the > > registers for configuring their watermarks, are double buffered. New > > values written to them won't take effect until said registers are > > "armed", which is done by writing to the PLANE_SURF (or in the case of > > cursor planes, the CURBASE register) register. > > > > With this in mind, up until now we've been updating watermarks on skl > > like this: > > > > non-modeset { > > - calculate (during atomic check phase) > > - finish_atomic_commit: > > - intel_pre_plane_update: > > - intel_update_watermarks() > > - {vblank happens; new watermarks + old plane values => underrun } > > - drm_atomic_helper_commit_planes_on_crtc: > > - start vblank evasion > > - write new plane registers > > - end vblank evasion > > } > > > > or > > > > modeset { > > - calculate (during atomic check phase) > > - finish_atomic_commit: > > - crtc_enable: > > - intel_update_watermarks() > > - {vblank happens; new watermarks + old plane values => underrun } > > - drm_atomic_helper_commit_planes_on_crtc: > > - start vblank evasion > > - write new plane registers > > - end vblank evasion > > } > > > > Now we update watermarks atomically like this: > > > > non-modeset { > > - calculate (during atomic check phase) > > - finish_atomic_commit: > > - intel_pre_plane_update: > > - intel_update_watermarks() (wm values aren't written yet) > > - drm_atomic_helper_commit_planes_on_crtc: > > - start vblank evasion > > - write new plane registers > > - write new wm values > > - end vblank evasion > > } > > > > modeset { > > - calculate (during atomic check phase) > > - finish_atomic_commit: > > - crtc_enable: > > - intel_update_watermarks() (actual wm values aren't written > > yet) > > - drm_atomic_helper_commit_planes_on_crtc: > > - start vblank evasion > > - write new plane registers > > - write new wm values > > - end vblank evasion > > } > > > > So this patch moves all of the watermark writes into the right place; > > inside of the vblank evasion where we update all of the registers for > > each plane. While this patch doesn't fix everything, it does allow us to > > update the watermark values in the way the hardware expects us to. > > > > Changes since original patch series: > > - Remove mutex_lock/mutex_unlock since they don't do anything and we're > > not touching global state > > - Move skl_write_cursor_wm/skl_write_plane_wm functions into > > intel_pm.c, make externally visible > > - Add skl_write_plane_wm calls to skl_update_plane > > - Fix conditional for for loop in skl_write_plane_wm (level < max_level > > should be level <= max_level) > > - Make diagram in commit more accurate to what's actually happening > > - Add Fixes: > > > > Changes since v1: > > - Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more > > then just Skylake > > - Update description to make it clear this patch doesn't fix everything > > - Check if pipes were actually changed before writing watermarks > > > > Changes since v2: > > - Write PIPE_WM_LINETIME during vblank evasion > > > > Changes since v3: > > - Rebase against new SAGV patch changes > > > > Changes since v4: > > - Add a parameter to choose what skl_wm_values struct to use when > > writing new plane watermarks > > > > Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation") > > Signed-off-by: Lyude > > Cc: stable@vger.kernel.org > > Cc: Ville Syrjälä > > Cc: Daniel Vetter > > Cc: Radhakrishna Sripada > > Cc: Hans de Goede > > Cc: Matt Roper I imagine we'll eventually probably want to create a new display vfunc to handle platform-specific pipe-level stuff that needs to happen under vblank evasion (like the scalers and linetime WM we have today) to keep the code clean; maybe add a TODO comment to that effect? Anyway, this looks good enough for now, so Reviewed-by: Matt Roper > > --- > > drivers/gpu/drm/i915/intel_display.c | 8 +++++ > > drivers/gpu/drm/i915/intel_drv.h | 5 ++++ > > drivers/gpu/drm/i915/intel_pm.c | 58 ++++++++++++++++++++++++++---------- > > drivers/gpu/drm/i915/intel_sprite.c | 6 ++++ > > 4 files changed, 61 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 76ba79f..79d146c 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -2980,6 +2980,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane, > > struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); > > struct drm_framebuffer *fb = plane_state->base.fb; > > struct drm_i915_gem_object *obj = intel_fb_obj(fb); > > + struct skl_wm_values *wm = &dev_priv->wm.skl_results; > > int pipe = intel_crtc->pipe; > > u32 plane_ctl, stride_div, stride; > > u32 tile_height, plane_offset, plane_size; > > @@ -3031,6 +3032,9 @@ static void skylake_update_primary_plane(struct drm_plane *plane, > > intel_crtc->adjusted_x = x_offset; > > intel_crtc->adjusted_y = y_offset; > > > > + if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) > > + skl_write_plane_wm(intel_crtc, wm, 0); > > + > > I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); > > I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); > > I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); > > @@ -10243,9 +10247,13 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, > > struct drm_device *dev = crtc->dev; > > struct drm_i915_private *dev_priv = to_i915(dev); > > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > > + struct skl_wm_values *wm = &dev_priv->wm.skl_results; > > int pipe = intel_crtc->pipe; > > uint32_t cntl = 0; > > > > + if (IS_GEN9(dev_priv) && wm->dirty_pipes & drm_crtc_mask(crtc)) > > + skl_write_cursor_wm(intel_crtc, wm); > > + > > if (plane_state && plane_state->visible) { > > cntl = MCURSOR_GAMMA_ENABLE; > > switch (plane_state->base.crtc_w) { > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > index 6b0532a..1b444d3 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -1711,6 +1711,11 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, > > struct skl_ddb_allocation *ddb /* out */); > > int skl_enable_sagv(struct drm_i915_private *dev_priv); > > int skl_disable_sagv(struct drm_i915_private *dev_priv); > > +void skl_write_cursor_wm(struct intel_crtc *intel_crtc, > > + const struct skl_wm_values *wm); > > +void skl_write_plane_wm(struct intel_crtc *intel_crtc, > > + const struct skl_wm_values *wm, > > + int plane); > > uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); > > bool ilk_disable_lp_wm(struct drm_device *dev); > > int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 7fd299e..53adcbf 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3798,6 +3798,47 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, > > I915_WRITE(reg, 0); > > } > > > > +void skl_write_plane_wm(struct intel_crtc *intel_crtc, > > + const struct skl_wm_values *wm, > > + int plane) > > +{ > > + struct drm_crtc *crtc = &intel_crtc->base; > > + struct drm_device *dev = crtc->dev; > > + struct drm_i915_private *dev_priv = to_i915(dev); > > + int level, max_level = ilk_wm_max_level(dev); > > + enum pipe pipe = intel_crtc->pipe; > > + > > + if (!(wm->dirty_pipes & drm_crtc_mask(crtc))) > > + return; > > + > > + I915_WRITE(PIPE_WM_LINETIME(pipe), wm->wm_linetime[pipe]); > > I think I mentioned this on the previous version, but if we program this > here then it only gets programmed when a plane is being updated. It's > possible that we could have the linetime value change due to a scaler > update or a modeset, but without corresponding plane updates (e.g., > maybe all planes are off). So we probably need to make sure this value > gets written outside the plane updates (but still under vblank evasion). > > > + > > + for (level = 0; level <= max_level; level++) { > > + I915_WRITE(PLANE_WM(pipe, plane, level), > > + wm->plane[pipe][plane][level]); > > + } > > + I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]); > > I notice that you moved the DDB update into skl_write_cursor_wm() down > below, but didn't move the plane DDB update in here. I realize you > remedy that in patch #6 where you finally fix up the flushing order, but > the inconsistency between how cursor vs !cursor planes are handled seems > confusing. Can we either move the plane DDB update here in this patch > (we don't flush properly yet, but we're really no worse off than we > already are), or can we defer the move of the cursor DDB to patch 6 to > keep them consistent? > > > Matt > > > +} > > + > > +void skl_write_cursor_wm(struct intel_crtc *intel_crtc, > > + const struct skl_wm_values *wm) > > +{ > > + struct drm_crtc *crtc = &intel_crtc->base; > > + struct drm_device *dev = crtc->dev; > > + struct drm_i915_private *dev_priv = to_i915(dev); > > + int level, max_level = ilk_wm_max_level(dev); > > + enum pipe pipe = intel_crtc->pipe; > > + > > + for (level = 0; level <= max_level; level++) { > > + I915_WRITE(CUR_WM(pipe, level), > > + wm->plane[pipe][PLANE_CURSOR][level]); > > + } > > + I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]); > > + > > + skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), > > + &wm->ddb.plane[pipe][PLANE_CURSOR]); > > +} > > + > > static void skl_write_wm_values(struct drm_i915_private *dev_priv, > > const struct skl_wm_values *new) > > { > > @@ -3805,7 +3846,7 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, > > struct intel_crtc *crtc; > > > > for_each_intel_crtc(dev, crtc) { > > - int i, level, max_level = ilk_wm_max_level(dev); > > + int i; > > enum pipe pipe = crtc->pipe; > > > > if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0) > > @@ -3813,21 +3854,6 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, > > if (!crtc->active) > > continue; > > > > - I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); > > - > > - for (level = 0; level <= max_level; level++) { > > - for (i = 0; i < intel_num_planes(crtc); i++) > > - I915_WRITE(PLANE_WM(pipe, i, level), > > - new->plane[pipe][i][level]); > > - I915_WRITE(CUR_WM(pipe, level), > > - new->plane[pipe][PLANE_CURSOR][level]); > > - } > > - for (i = 0; i < intel_num_planes(crtc); i++) > > - I915_WRITE(PLANE_WM_TRANS(pipe, i), > > - new->plane_trans[pipe][i]); > > - I915_WRITE(CUR_WM_TRANS(pipe), > > - new->plane_trans[pipe][PLANE_CURSOR]); > > - > > for (i = 0; i < intel_num_planes(crtc); i++) { > > skl_ddb_entry_write(dev_priv, > > PLANE_BUF_CFG(pipe, i), > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > > index 0de935a..55d173f 100644 > > --- a/drivers/gpu/drm/i915/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/intel_sprite.c > > @@ -203,6 +203,9 @@ skl_update_plane(struct drm_plane *drm_plane, > > struct intel_plane *intel_plane = to_intel_plane(drm_plane); > > struct drm_framebuffer *fb = plane_state->base.fb; > > struct drm_i915_gem_object *obj = intel_fb_obj(fb); > > + struct skl_wm_values *wm = &dev_priv->wm.skl_results; > > + struct drm_crtc *crtc = crtc_state->base.crtc; > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > > const int pipe = intel_plane->pipe; > > const int plane = intel_plane->plane + 1; > > u32 plane_ctl, stride_div, stride; > > @@ -238,6 +241,9 @@ skl_update_plane(struct drm_plane *drm_plane, > > crtc_w--; > > crtc_h--; > > > > + if (wm->dirty_pipes & drm_crtc_mask(crtc)) > > + skl_write_plane_wm(intel_crtc, wm, plane); > > + > > if (key->flags) { > > I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); > > I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); > > -- > > 2.7.4 > > > > -- > Matt Roper > Graphics Software Engineer > IoTG Platform Enabling & Development > Intel Corporation > (916) 356-2795 -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com ([134.134.136.20]:3155 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756802AbcHCVPt (ORCPT ); Wed, 3 Aug 2016 17:15:49 -0400 Date: Wed, 3 Aug 2016 14:14:53 -0700 From: Matt Roper To: Lyude Cc: intel-gfx@lists.freedesktop.org, Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Maarten Lankhorst , stable@vger.kernel.org, Daniel Vetter , Radhakrishna Sripada , Hans de Goede , Jani Nikula , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 3/6] drm/i915/skl: Update plane watermarks atomically during plane updates Message-ID: <20160803211453.GA871@intel.com> References: <1470163975-30467-1-git-send-email-cpaul@redhat.com> <1470163975-30467-4-git-send-email-cpaul@redhat.com> <20160802212033.GY32025@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20160802212033.GY32025@intel.com> Sender: stable-owner@vger.kernel.org List-ID: On Tue, Aug 02, 2016 at 02:20:33PM -0700, Matt Roper wrote: > On Tue, Aug 02, 2016 at 02:52:51PM -0400, Lyude wrote: > > Thanks to Ville for suggesting this as a potential solution to pipe > > underruns on Skylake. > > > > On Skylake all of the registers for configuring planes, including the > > registers for configuring their watermarks, are double buffered. New > > values written to them won't take effect until said registers are > > "armed", which is done by writing to the PLANE_SURF (or in the case of > > cursor planes, the CURBASE register) register. > > > > With this in mind, up until now we've been updating watermarks on skl > > like this: > > > > non-modeset { > > - calculate (during atomic check phase) > > - finish_atomic_commit: > > - intel_pre_plane_update: > > - intel_update_watermarks() > > - {vblank happens; new watermarks + old plane values => underrun } > > - drm_atomic_helper_commit_planes_on_crtc: > > - start vblank evasion > > - write new plane registers > > - end vblank evasion > > } > > > > or > > > > modeset { > > - calculate (during atomic check phase) > > - finish_atomic_commit: > > - crtc_enable: > > - intel_update_watermarks() > > - {vblank happens; new watermarks + old plane values => underrun } > > - drm_atomic_helper_commit_planes_on_crtc: > > - start vblank evasion > > - write new plane registers > > - end vblank evasion > > } > > > > Now we update watermarks atomically like this: > > > > non-modeset { > > - calculate (during atomic check phase) > > - finish_atomic_commit: > > - intel_pre_plane_update: > > - intel_update_watermarks() (wm values aren't written yet) > > - drm_atomic_helper_commit_planes_on_crtc: > > - start vblank evasion > > - write new plane registers > > - write new wm values > > - end vblank evasion > > } > > > > modeset { > > - calculate (during atomic check phase) > > - finish_atomic_commit: > > - crtc_enable: > > - intel_update_watermarks() (actual wm values aren't written > > yet) > > - drm_atomic_helper_commit_planes_on_crtc: > > - start vblank evasion > > - write new plane registers > > - write new wm values > > - end vblank evasion > > } > > > > So this patch moves all of the watermark writes into the right place; > > inside of the vblank evasion where we update all of the registers for > > each plane. While this patch doesn't fix everything, it does allow us to > > update the watermark values in the way the hardware expects us to. > > > > Changes since original patch series: > > - Remove mutex_lock/mutex_unlock since they don't do anything and we're > > not touching global state > > - Move skl_write_cursor_wm/skl_write_plane_wm functions into > > intel_pm.c, make externally visible > > - Add skl_write_plane_wm calls to skl_update_plane > > - Fix conditional for for loop in skl_write_plane_wm (level < max_level > > should be level <= max_level) > > - Make diagram in commit more accurate to what's actually happening > > - Add Fixes: > > > > Changes since v1: > > - Use IS_GEN9() instead of IS_SKYLAKE() since these fixes apply to more > > then just Skylake > > - Update description to make it clear this patch doesn't fix everything > > - Check if pipes were actually changed before writing watermarks > > > > Changes since v2: > > - Write PIPE_WM_LINETIME during vblank evasion > > > > Changes since v3: > > - Rebase against new SAGV patch changes > > > > Changes since v4: > > - Add a parameter to choose what skl_wm_values struct to use when > > writing new plane watermarks > > > > Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation") > > Signed-off-by: Lyude > > Cc: stable@vger.kernel.org > > Cc: Ville Syrj�l� > > Cc: Daniel Vetter > > Cc: Radhakrishna Sripada > > Cc: Hans de Goede > > Cc: Matt Roper I imagine we'll eventually probably want to create a new display vfunc to handle platform-specific pipe-level stuff that needs to happen under vblank evasion (like the scalers and linetime WM we have today) to keep the code clean; maybe add a TODO comment to that effect? Anyway, this looks good enough for now, so Reviewed-by: Matt Roper > > --- > > drivers/gpu/drm/i915/intel_display.c | 8 +++++ > > drivers/gpu/drm/i915/intel_drv.h | 5 ++++ > > drivers/gpu/drm/i915/intel_pm.c | 58 ++++++++++++++++++++++++++---------- > > drivers/gpu/drm/i915/intel_sprite.c | 6 ++++ > > 4 files changed, 61 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > > index 76ba79f..79d146c 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -2980,6 +2980,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane, > > struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); > > struct drm_framebuffer *fb = plane_state->base.fb; > > struct drm_i915_gem_object *obj = intel_fb_obj(fb); > > + struct skl_wm_values *wm = &dev_priv->wm.skl_results; > > int pipe = intel_crtc->pipe; > > u32 plane_ctl, stride_div, stride; > > u32 tile_height, plane_offset, plane_size; > > @@ -3031,6 +3032,9 @@ static void skylake_update_primary_plane(struct drm_plane *plane, > > intel_crtc->adjusted_x = x_offset; > > intel_crtc->adjusted_y = y_offset; > > > > + if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) > > + skl_write_plane_wm(intel_crtc, wm, 0); > > + > > I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); > > I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); > > I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); > > @@ -10243,9 +10247,13 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, > > struct drm_device *dev = crtc->dev; > > struct drm_i915_private *dev_priv = to_i915(dev); > > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > > + struct skl_wm_values *wm = &dev_priv->wm.skl_results; > > int pipe = intel_crtc->pipe; > > uint32_t cntl = 0; > > > > + if (IS_GEN9(dev_priv) && wm->dirty_pipes & drm_crtc_mask(crtc)) > > + skl_write_cursor_wm(intel_crtc, wm); > > + > > if (plane_state && plane_state->visible) { > > cntl = MCURSOR_GAMMA_ENABLE; > > switch (plane_state->base.crtc_w) { > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > index 6b0532a..1b444d3 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -1711,6 +1711,11 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, > > struct skl_ddb_allocation *ddb /* out */); > > int skl_enable_sagv(struct drm_i915_private *dev_priv); > > int skl_disable_sagv(struct drm_i915_private *dev_priv); > > +void skl_write_cursor_wm(struct intel_crtc *intel_crtc, > > + const struct skl_wm_values *wm); > > +void skl_write_plane_wm(struct intel_crtc *intel_crtc, > > + const struct skl_wm_values *wm, > > + int plane); > > uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); > > bool ilk_disable_lp_wm(struct drm_device *dev); > > int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6); > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index 7fd299e..53adcbf 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3798,6 +3798,47 @@ static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, > > I915_WRITE(reg, 0); > > } > > > > +void skl_write_plane_wm(struct intel_crtc *intel_crtc, > > + const struct skl_wm_values *wm, > > + int plane) > > +{ > > + struct drm_crtc *crtc = &intel_crtc->base; > > + struct drm_device *dev = crtc->dev; > > + struct drm_i915_private *dev_priv = to_i915(dev); > > + int level, max_level = ilk_wm_max_level(dev); > > + enum pipe pipe = intel_crtc->pipe; > > + > > + if (!(wm->dirty_pipes & drm_crtc_mask(crtc))) > > + return; > > + > > + I915_WRITE(PIPE_WM_LINETIME(pipe), wm->wm_linetime[pipe]); > > I think I mentioned this on the previous version, but if we program this > here then it only gets programmed when a plane is being updated. It's > possible that we could have the linetime value change due to a scaler > update or a modeset, but without corresponding plane updates (e.g., > maybe all planes are off). So we probably need to make sure this value > gets written outside the plane updates (but still under vblank evasion). > > > + > > + for (level = 0; level <= max_level; level++) { > > + I915_WRITE(PLANE_WM(pipe, plane, level), > > + wm->plane[pipe][plane][level]); > > + } > > + I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]); > > I notice that you moved the DDB update into skl_write_cursor_wm() down > below, but didn't move the plane DDB update in here. I realize you > remedy that in patch #6 where you finally fix up the flushing order, but > the inconsistency between how cursor vs !cursor planes are handled seems > confusing. Can we either move the plane DDB update here in this patch > (we don't flush properly yet, but we're really no worse off than we > already are), or can we defer the move of the cursor DDB to patch 6 to > keep them consistent? > > > Matt > > > +} > > + > > +void skl_write_cursor_wm(struct intel_crtc *intel_crtc, > > + const struct skl_wm_values *wm) > > +{ > > + struct drm_crtc *crtc = &intel_crtc->base; > > + struct drm_device *dev = crtc->dev; > > + struct drm_i915_private *dev_priv = to_i915(dev); > > + int level, max_level = ilk_wm_max_level(dev); > > + enum pipe pipe = intel_crtc->pipe; > > + > > + for (level = 0; level <= max_level; level++) { > > + I915_WRITE(CUR_WM(pipe, level), > > + wm->plane[pipe][PLANE_CURSOR][level]); > > + } > > + I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]); > > + > > + skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), > > + &wm->ddb.plane[pipe][PLANE_CURSOR]); > > +} > > + > > static void skl_write_wm_values(struct drm_i915_private *dev_priv, > > const struct skl_wm_values *new) > > { > > @@ -3805,7 +3846,7 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, > > struct intel_crtc *crtc; > > > > for_each_intel_crtc(dev, crtc) { > > - int i, level, max_level = ilk_wm_max_level(dev); > > + int i; > > enum pipe pipe = crtc->pipe; > > > > if ((new->dirty_pipes & drm_crtc_mask(&crtc->base)) == 0) > > @@ -3813,21 +3854,6 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv, > > if (!crtc->active) > > continue; > > > > - I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); > > - > > - for (level = 0; level <= max_level; level++) { > > - for (i = 0; i < intel_num_planes(crtc); i++) > > - I915_WRITE(PLANE_WM(pipe, i, level), > > - new->plane[pipe][i][level]); > > - I915_WRITE(CUR_WM(pipe, level), > > - new->plane[pipe][PLANE_CURSOR][level]); > > - } > > - for (i = 0; i < intel_num_planes(crtc); i++) > > - I915_WRITE(PLANE_WM_TRANS(pipe, i), > > - new->plane_trans[pipe][i]); > > - I915_WRITE(CUR_WM_TRANS(pipe), > > - new->plane_trans[pipe][PLANE_CURSOR]); > > - > > for (i = 0; i < intel_num_planes(crtc); i++) { > > skl_ddb_entry_write(dev_priv, > > PLANE_BUF_CFG(pipe, i), > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > > index 0de935a..55d173f 100644 > > --- a/drivers/gpu/drm/i915/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/intel_sprite.c > > @@ -203,6 +203,9 @@ skl_update_plane(struct drm_plane *drm_plane, > > struct intel_plane *intel_plane = to_intel_plane(drm_plane); > > struct drm_framebuffer *fb = plane_state->base.fb; > > struct drm_i915_gem_object *obj = intel_fb_obj(fb); > > + struct skl_wm_values *wm = &dev_priv->wm.skl_results; > > + struct drm_crtc *crtc = crtc_state->base.crtc; > > + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > > const int pipe = intel_plane->pipe; > > const int plane = intel_plane->plane + 1; > > u32 plane_ctl, stride_div, stride; > > @@ -238,6 +241,9 @@ skl_update_plane(struct drm_plane *drm_plane, > > crtc_w--; > > crtc_h--; > > > > + if (wm->dirty_pipes & drm_crtc_mask(crtc)) > > + skl_write_plane_wm(intel_crtc, wm, plane); > > + > > if (key->flags) { > > I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); > > I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); > > -- > > 2.7.4 > > > > -- > Matt Roper > Graphics Software Engineer > IoTG Platform Enabling & Development > Intel Corporation > (916) 356-2795 -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795