diff for duplicates of <20160808115651.GO5243@dell> diff --git a/a/1.txt b/N1/1.txt index 119d31b..e366801 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,27 +4,26 @@ On Fri, 08 Jul 2016, Alexandre Belloni wrote: > > The AC100's RTC side has 3 clock outputs on external pins, which can > > provide a clock signal to the SoC or other modules, such as WiFi or > > GSM modules. -> >=20 +> > > > Support this with a custom clk driver integrated with the rtc driver. -> >=20 +> > > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> ->=20 +> > > --- > > Changes since v4: none -> >=20 +> > > > Changes since v3: -> >=20 +> > > > - Renamed clk32k prefixes to clkout, except for the internal 32k clk > > - Changed default clk output names to "ac100-cko{1,2,3}-rtc" > > - Moved 4M ADDA clk to codec side -> >=20 +> > > > Changes since v2: none > > Changes since v1: none -> >=20 +> > > > --- -> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++= -++++++++ +> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 302 insertions(+) Applied, thanks. @@ -35,7 +34,7 @@ Applied, thanks. > > +++ b/drivers/rtc/rtc-ac100.c > > @@ -16,6 +16,7 @@ > > */ -> > =20 +> > > > #include <linux/bcd.h> > > +#include <linux/clk-provider.h> > > #include <linux/device.h> @@ -44,7 +43,7 @@ Applied, thanks. > > @@ -31,6 +32,15 @@ > > /* Control register */ > > #define AC100_RTC_CTRL_24HOUR BIT(0) -> > =20 +> > > > +/* Clock output register bits */ > > +#define AC100_CLKOUT_PRE_DIV_SHIFT 5 > > +#define AC100_CLKOUT_PRE_DIV_WIDTH 3 @@ -60,21 +59,20 @@ Applied, thanks. > > @@ -67,14 +77,292 @@ > > #define AC100_YEAR_MAX 2069 > > #define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900) -> > =20 +> > > > +struct ac100_clkout { > > + struct clk_hw hw; > > + struct regmap *regmap; > > + u8 offset; > > +}; > > + -> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw= -) +> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw) > > + > > +#define AC100_RTC_32K_NAME "ac100-rtc-32k" > > +#define AC100_RTC_32K_RATE 32768 > > +#define AC100_CLKOUT_NUM 3 > > + -> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] =3D { +> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = { > > + "ac100-cko1-rtc", > > + "ac100-cko2-rtc", > > + "ac100-cko3-rtc", @@ -91,69 +89,67 @@ Applied, thanks. > > + struct ac100_clkout clks[AC100_CLKOUT_NUM]; > > + struct clk_hw_onecell_data *clk_data; > > }; -> > =20 +> > > > +/** > > + * Clock controls for 3 clock output pins > > + */ > > + -> > +static const struct clk_div_table ac100_clkout_prediv[] =3D { -> > + { .val =3D 0, .div =3D 1 }, -> > + { .val =3D 1, .div =3D 2 }, -> > + { .val =3D 2, .div =3D 4 }, -> > + { .val =3D 3, .div =3D 8 }, -> > + { .val =3D 4, .div =3D 16 }, -> > + { .val =3D 5, .div =3D 32 }, -> > + { .val =3D 6, .div =3D 64 }, -> > + { .val =3D 7, .div =3D 122 }, +> > +static const struct clk_div_table ac100_clkout_prediv[] = { +> > + { .val = 0, .div = 1 }, +> > + { .val = 1, .div = 2 }, +> > + { .val = 2, .div = 4 }, +> > + { .val = 3, .div = 8 }, +> > + { .val = 4, .div = 16 }, +> > + { .val = 5, .div = 32 }, +> > + { .val = 6, .div = 64 }, +> > + { .val = 7, .div = 122 }, > > + { }, > > +}; > > + -> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz = -*/ +> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */ > > +static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw, > > + unsigned long prate) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg, div; > > + > > + regmap_read(clk->regmap, clk->offset, ®); > > + > > + /* Handle pre-divider first */ -> > + if (prate !=3D AC100_RTC_32K_RATE) { -> > + div =3D (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) & +> > + if (prate != AC100_RTC_32K_RATE) { +> > + div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) & > > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1); -> > + prate =3D divider_recalc_rate(hw, prate, div, +> > + prate = divider_recalc_rate(hw, prate, div, > > + ac100_clkout_prediv, 0); > > + } > > + -> > + div =3D (reg >> AC100_CLKOUT_DIV_SHIFT) & +> > + div = (reg >> AC100_CLKOUT_DIV_SHIFT) & > > + (BIT(AC100_CLKOUT_DIV_WIDTH) - 1); > > + return divider_recalc_rate(hw, prate, div, NULL, > > + CLK_DIVIDER_POWER_OF_TWO); > > +} > > + -> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long r= -ate, +> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long prate) > > +{ -> > + unsigned long best_rate =3D 0, tmp_rate, tmp_prate; +> > + unsigned long best_rate = 0, tmp_rate, tmp_prate; > > + int i; > > + -> > + if (prate =3D=3D AC100_RTC_32K_RATE) +> > + if (prate == AC100_RTC_32K_RATE) > > + return divider_round_rate(hw, rate, &prate, NULL, > > + AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); > > + -> > + for (i =3D 0; ac100_clkout_prediv[i].div; i++) { -> > + tmp_prate =3D DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); -> > + tmp_rate =3D divider_round_rate(hw, rate, &tmp_prate, NULL, +> > + for (i = 0; ac100_clkout_prediv[i].div; i++) { +> > + tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); +> > + tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL, > > + AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); > > + > > + if (tmp_rate > rate) > > + continue; > > + if (rate - tmp_rate < best_rate - tmp_rate) -> > + best_rate =3D tmp_rate; +> > + best_rate = tmp_rate; > > + } > > + > > + return best_rate; @@ -163,58 +159,56 @@ ate, > > + struct clk_rate_request *req) > > +{ > > + struct clk_hw *best_parent; -> > + unsigned long best =3D 0; -> > + int i, num_parents =3D clk_hw_get_num_parents(hw); +> > + unsigned long best = 0; +> > + int i, num_parents = clk_hw_get_num_parents(hw); > > + -> > + for (i =3D 0; i < num_parents; i++) { -> > + struct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i); -> > + unsigned long tmp, prate =3D clk_hw_get_rate(parent); +> > + for (i = 0; i < num_parents; i++) { +> > + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); +> > + unsigned long tmp, prate = clk_hw_get_rate(parent); > > + -> > + tmp =3D ac100_clkout_round_rate(hw, req->rate, prate); +> > + tmp = ac100_clkout_round_rate(hw, req->rate, prate); > > + > > + if (tmp > req->rate) > > + continue; > > + if (req->rate - tmp < req->rate - best) { -> > + best =3D tmp; -> > + best_parent =3D parent; +> > + best = tmp; +> > + best_parent = parent; > > + } > > + } > > + > > + if (!best) > > + return -EINVAL; > > + -> > + req->best_parent_hw =3D best_parent; -> > + req->best_parent_rate =3D best; -> > + req->rate =3D best; +> > + req->best_parent_hw = best_parent; +> > + req->best_parent_rate = best; +> > + req->rate = best; > > + > > + return 0; > > +} > > + -> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate= -, +> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long prate) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); -> > + int div =3D 0, pre_div =3D 0; +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); +> > + int div = 0, pre_div = 0; > > + > > + do { -> > + div =3D divider_get_val(rate * ac100_clkout_prediv[pre_div].div, +> > + div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div, > > + prate, NULL, AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); -> > + if (div >=3D 0) +> > + if (div >= 0) > > + break; -> > + } while (prate !=3D AC100_RTC_32K_RATE && +> > + } while (prate != AC100_RTC_32K_RATE && > > + ac100_clkout_prediv[++pre_div].div); > > + > > + if (div < 0) > > + return div; > > + -> > + pre_div =3D ac100_clkout_prediv[pre_div].val; +> > + pre_div = ac100_clkout_prediv[pre_div].val; > > + > > + regmap_update_bits(clk->regmap, clk->offset, > > + ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT | -> > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_= -SHIFT, +> > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT, > > + (div - 1) << AC100_CLKOUT_DIV_SHIFT | > > + (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT); > > + @@ -223,7 +217,7 @@ SHIFT, > > + > > +static int ac100_clkout_prepare(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, > > + AC100_CLKOUT_EN); @@ -231,14 +225,14 @@ SHIFT, > > + > > +static void ac100_clkout_unprepare(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0); > > +} > > + > > +static int ac100_clkout_is_prepared(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg; > > + > > + regmap_read(clk->regmap, clk->offset, ®); @@ -248,7 +242,7 @@ SHIFT, > > + > > +static u8 ac100_clkout_get_parent(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg; > > + > > + regmap_read(clk->regmap, clk->offset, ®); @@ -258,81 +252,80 @@ SHIFT, > > + > > +static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + return regmap_update_bits(clk->regmap, clk->offset, > > + BIT(AC100_CLKOUT_MUX_SHIFT), > > + index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0); > > +} > > + -> > +static const struct clk_ops ac100_clkout_ops =3D { -> > + .prepare =3D ac100_clkout_prepare, -> > + .unprepare =3D ac100_clkout_unprepare, -> > + .is_prepared =3D ac100_clkout_is_prepared, -> > + .recalc_rate =3D ac100_clkout_recalc_rate, -> > + .determine_rate =3D ac100_clkout_determine_rate, -> > + .get_parent =3D ac100_clkout_get_parent, -> > + .set_parent =3D ac100_clkout_set_parent, -> > + .set_rate =3D ac100_clkout_set_rate, +> > +static const struct clk_ops ac100_clkout_ops = { +> > + .prepare = ac100_clkout_prepare, +> > + .unprepare = ac100_clkout_unprepare, +> > + .is_prepared = ac100_clkout_is_prepared, +> > + .recalc_rate = ac100_clkout_recalc_rate, +> > + .determine_rate = ac100_clkout_determine_rate, +> > + .get_parent = ac100_clkout_get_parent, +> > + .set_parent = ac100_clkout_set_parent, +> > + .set_rate = ac100_clkout_set_rate, > > +}; > > + > > +static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip) > > +{ -> > + struct device_node *np =3D chip->dev->of_node; -> > + const char *parents[2] =3D {AC100_RTC_32K_NAME}; +> > + struct device_node *np = chip->dev->of_node; +> > + const char *parents[2] = {AC100_RTC_32K_NAME}; > > + int i, ret; > > + -> > + chip->clk_data =3D devm_kzalloc(chip->dev, sizeof(*chip->clk_data) + +> > + chip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) + > > + sizeof(*chip->clk_data->hws) * > > + AC100_CLKOUT_NUM, > > + GFP_KERNEL); > > + if (!chip->clk_data) > > + return -ENOMEM; > > + -> > + chip->rtc_32k_clk =3D clk_hw_register_fixed_rate(chip->dev, +> > + chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev, > > + AC100_RTC_32K_NAME, > > + NULL, 0, > > + AC100_RTC_32K_RATE); > > + if (IS_ERR(chip->rtc_32k_clk)) { -> > + ret =3D PTR_ERR(chip->rtc_32k_clk); +> > + ret = PTR_ERR(chip->rtc_32k_clk); > > + dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n", > > + ret); > > + return ret; > > + } > > + -> > + parents[1] =3D of_clk_get_parent_name(np, 0); +> > + parents[1] = of_clk_get_parent_name(np, 0); > > + if (!parents[1]) { > > + dev_err(chip->dev, "Failed to get ADDA 4M clock\n"); > > + return -EINVAL; > > + } > > + -> > + for (i =3D 0; i < AC100_CLKOUT_NUM; i++) { -> > + struct ac100_clkout *clk =3D &chip->clks[i]; -> > + struct clk_init_data init =3D { -> > + .name =3D ac100_clkout_names[i], -> > + .ops =3D &ac100_clkout_ops, -> > + .parent_names =3D parents, -> > + .num_parents =3D ARRAY_SIZE(parents), -> > + .flags =3D 0, +> > + for (i = 0; i < AC100_CLKOUT_NUM; i++) { +> > + struct ac100_clkout *clk = &chip->clks[i]; +> > + struct clk_init_data init = { +> > + .name = ac100_clkout_names[i], +> > + .ops = &ac100_clkout_ops, +> > + .parent_names = parents, +> > + .num_parents = ARRAY_SIZE(parents), +> > + .flags = 0, > > + }; > > + -> > + clk->regmap =3D chip->regmap; -> > + clk->offset =3D AC100_CLKOUT_CTRL1 + i; -> > + clk->hw.init =3D &init; +> > + clk->regmap = chip->regmap; +> > + clk->offset = AC100_CLKOUT_CTRL1 + i; +> > + clk->hw.init = &init; > > + -> > + ret =3D devm_clk_hw_register(chip->dev, &clk->hw); +> > + ret = devm_clk_hw_register(chip->dev, &clk->hw); > > + if (ret) { > > + dev_err(chip->dev, "Failed to register clk '%s': %d\n", > > + init.name, ret); > > + goto err_unregister_rtc_32k; > > + } > > + -> > + chip->clk_data->hws[i] =3D &clk->hw; +> > + chip->clk_data->hws[i] = &clk->hw; > > + } > > + -> > + chip->clk_data->num =3D i; -> > + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_d= -ata); +> > + chip->clk_data->num = i; +> > + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data); > > + if (ret) > > + goto err_unregister_rtc_32k; > > + @@ -353,60 +346,46 @@ ata); > > +/** > > + * RTC related bits > > + */ -> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc= -_tm) +> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm) > > { -> > struct ac100_rtc_dev *chip =3D dev_get_drvdata(dev); -> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device= - *pdev) +> > struct ac100_rtc_dev *chip = dev_get_drvdata(dev); +> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device *pdev) > > return PTR_ERR(chip->rtc); > > } -> > =20 -> > + ret =3D ac100_rtc_register_clks(chip); +> > +> > + ret = ac100_rtc_register_clks(chip); > > + if (ret) > > + return ret; > > + > > dev_info(&pdev->dev, "RTC enabled\n"); -> > =20 +> > > > return 0; > > } -> > =20 +> > > > +static int ac100_rtc_remove(struct platform_device *pdev) > > +{ -> > + struct ac100_rtc_dev *chip =3D platform_get_drvdata(pdev); +> > + struct ac100_rtc_dev *chip = platform_get_drvdata(pdev); > > + > > + ac100_rtc_unregister_clks(chip); > > + > > + return 0; > > +} > > + -> > static const struct of_device_id ac100_rtc_match[] =3D { -> > { .compatible =3D "x-powers,ac100-rtc" }, +> > static const struct of_device_id ac100_rtc_match[] = { +> > { .compatible = "x-powers,ac100-rtc" }, > > { }, > > @@ -313,6 +614,7 @@ MODULE_DEVICE_TABLE(of, ac100_rtc_match); -> > =20 -> > static struct platform_driver ac100_rtc_driver =3D { -> > .probe =3D ac100_rtc_probe, -> > + .remove =3D ac100_rtc_remove, -> > .driver =3D { -> > .name =3D "ac100-rtc", -> > .of_match_table =3D of_match_ptr(ac100_rtc_match), ->=20 +> > +> > static struct platform_driver ac100_rtc_driver = { +> > .probe = ac100_rtc_probe, +> > + .remove = ac100_rtc_remove, +> > .driver = { +> > .name = "ac100-rtc", +> > .of_match_table = of_match_ptr(ac100_rtc_match), +> ---=20 +-- Lee Jones Linaro STMicroelectronics Landing Team Lead -Linaro.org =E2=94=82 Open source software for ARM SoCs +Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog - ---=20 -You received this message because you are subscribed to "rtc-linux". -Membership options at http://groups.google.com/group/rtc-linux . -Please read http://groups.google.com/group/rtc-linux/web/checklist -before submitting a driver. ----=20 -You received this message because you are subscribed to the Google Groups "= -rtc-linux" group. -To unsubscribe from this group and stop receiving emails from it, send an e= -mail to rtc-linux+unsubscribe@googlegroups.com. -For more options, visit https://groups.google.com/d/optout. diff --git a/a/content_digest b/N1/content_digest index a5539bb..1c07dac 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,10 @@ "ref\01467988422-17934-1-git-send-email-wens@csie.org\0" "ref\01467988422-17934-5-git-send-email-wens@csie.org\0" "ref\020160708162932.GN22202@piout.net\0" - "From\0Lee Jones <lee.jones@linaro.org>\0" - "Subject\0[rtc-linux] Re: [PATCH v5 4/7] rtc: ac100: Add clk output support\0" + "From\0lee.jones@linaro.org (Lee Jones)\0" + "Subject\0[PATCH v5 4/7] rtc: ac100: Add clk output support\0" "Date\0Mon, 8 Aug 2016 12:56:51 +0100\0" - "To\0Alexandre Belloni <alexandre.belloni@free-electrons.com>\0" - "Cc\0Chen-Yu Tsai <wens@csie.org>" - Alessandro Zummo <a.zummo@towertech.it> - Maxime Ripard <maxime.ripard@free-electrons.com> - linux-kernel@vger.kernel.org - rtc-linux@googlegroups.com - devicetree@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Fri, 08 Jul 2016, Alexandre Belloni wrote:\n" @@ -20,27 +13,26 @@ "> > The AC100's RTC side has 3 clock outputs on external pins, which can\n" "> > provide a clock signal to the SoC or other modules, such as WiFi or\n" "> > GSM modules.\n" - "> >=20\n" + "> > \n" "> > Support this with a custom clk driver integrated with the rtc driver.\n" - "> >=20\n" + "> > \n" "> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>\n" "> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>\n" - ">=20\n" + "> \n" "> > ---\n" "> > Changes since v4: none\n" - "> >=20\n" + "> > \n" "> > Changes since v3:\n" - "> >=20\n" + "> > \n" "> > - Renamed clk32k prefixes to clkout, except for the internal 32k clk\n" "> > - Changed default clk output names to \"ac100-cko{1,2,3}-rtc\"\n" "> > - Moved 4M ADDA clk to codec side\n" - "> >=20\n" + "> > \n" "> > Changes since v2: none\n" "> > Changes since v1: none\n" - "> >=20\n" + "> > \n" "> > ---\n" - "> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++=\n" - "++++++++\n" + "> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++++\n" "> > 1 file changed, 302 insertions(+)\n" "\n" "Applied, thanks.\n" @@ -51,7 +43,7 @@ "> > +++ b/drivers/rtc/rtc-ac100.c\n" "> > @@ -16,6 +16,7 @@\n" "> > */\n" - "> > =20\n" + "> > \n" "> > #include <linux/bcd.h>\n" "> > +#include <linux/clk-provider.h>\n" "> > #include <linux/device.h>\n" @@ -60,7 +52,7 @@ "> > @@ -31,6 +32,15 @@\n" "> > /* Control register */\n" "> > #define AC100_RTC_CTRL_24HOUR\tBIT(0)\n" - "> > =20\n" + "> > \n" "> > +/* Clock output register bits */\n" "> > +#define AC100_CLKOUT_PRE_DIV_SHIFT\t5\n" "> > +#define AC100_CLKOUT_PRE_DIV_WIDTH\t3\n" @@ -76,21 +68,20 @@ "> > @@ -67,14 +77,292 @@\n" "> > #define AC100_YEAR_MAX\t\t\t\t2069\n" "> > #define AC100_YEAR_OFF\t\t\t\t(AC100_YEAR_MIN - 1900)\n" - "> > =20\n" + "> > \n" "> > +struct ac100_clkout {\n" "> > +\tstruct clk_hw hw;\n" "> > +\tstruct regmap *regmap;\n" "> > +\tu8 offset;\n" "> > +};\n" "> > +\n" - "> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw=\n" - ")\n" + "> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)\n" "> > +\n" "> > +#define AC100_RTC_32K_NAME\t\"ac100-rtc-32k\"\n" "> > +#define AC100_RTC_32K_RATE\t32768\n" "> > +#define AC100_CLKOUT_NUM\t3\n" "> > +\n" - "> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] =3D {\n" + "> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {\n" "> > +\t\"ac100-cko1-rtc\",\n" "> > +\t\"ac100-cko2-rtc\",\n" "> > +\t\"ac100-cko3-rtc\",\n" @@ -107,69 +98,67 @@ "> > +\tstruct ac100_clkout clks[AC100_CLKOUT_NUM];\n" "> > +\tstruct clk_hw_onecell_data *clk_data;\n" "> > };\n" - "> > =20\n" + "> > \n" "> > +/**\n" "> > + * Clock controls for 3 clock output pins\n" "> > + */\n" "> > +\n" - "> > +static const struct clk_div_table ac100_clkout_prediv[] =3D {\n" - "> > +\t{ .val =3D 0, .div =3D 1 },\n" - "> > +\t{ .val =3D 1, .div =3D 2 },\n" - "> > +\t{ .val =3D 2, .div =3D 4 },\n" - "> > +\t{ .val =3D 3, .div =3D 8 },\n" - "> > +\t{ .val =3D 4, .div =3D 16 },\n" - "> > +\t{ .val =3D 5, .div =3D 32 },\n" - "> > +\t{ .val =3D 6, .div =3D 64 },\n" - "> > +\t{ .val =3D 7, .div =3D 122 },\n" + "> > +static const struct clk_div_table ac100_clkout_prediv[] = {\n" + "> > +\t{ .val = 0, .div = 1 },\n" + "> > +\t{ .val = 1, .div = 2 },\n" + "> > +\t{ .val = 2, .div = 4 },\n" + "> > +\t{ .val = 3, .div = 8 },\n" + "> > +\t{ .val = 4, .div = 16 },\n" + "> > +\t{ .val = 5, .div = 32 },\n" + "> > +\t{ .val = 6, .div = 64 },\n" + "> > +\t{ .val = 7, .div = 122 },\n" "> > +\t{ },\n" "> > +};\n" "> > +\n" - "> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz =\n" - "*/\n" + "> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */\n" "> > +static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,\n" "> > +\t\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg, div;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" "> > +\n" "> > +\t/* Handle pre-divider first */\n" - "> > +\tif (prate !=3D AC100_RTC_32K_RATE) {\n" - "> > +\t\tdiv =3D (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &\n" + "> > +\tif (prate != AC100_RTC_32K_RATE) {\n" + "> > +\t\tdiv = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &\n" "> > +\t\t\t((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);\n" - "> > +\t\tprate =3D divider_recalc_rate(hw, prate, div,\n" + "> > +\t\tprate = divider_recalc_rate(hw, prate, div,\n" "> > +\t\t\t\t\t ac100_clkout_prediv, 0);\n" "> > +\t}\n" "> > +\n" - "> > +\tdiv =3D (reg >> AC100_CLKOUT_DIV_SHIFT) &\n" + "> > +\tdiv = (reg >> AC100_CLKOUT_DIV_SHIFT) &\n" "> > +\t\t(BIT(AC100_CLKOUT_DIV_WIDTH) - 1);\n" "> > +\treturn divider_recalc_rate(hw, prate, div, NULL,\n" "> > +\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +}\n" "> > +\n" - "> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long r=\n" - "ate,\n" + "> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,\n" "> > +\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tunsigned long best_rate =3D 0, tmp_rate, tmp_prate;\n" + "> > +\tunsigned long best_rate = 0, tmp_rate, tmp_prate;\n" "> > +\tint i;\n" "> > +\n" - "> > +\tif (prate =3D=3D AC100_RTC_32K_RATE)\n" + "> > +\tif (prate == AC100_RTC_32K_RATE)\n" "> > +\t\treturn divider_round_rate(hw, rate, &prate, NULL,\n" "> > +\t\t\t\t\t AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +\n" - "> > +\tfor (i =3D 0; ac100_clkout_prediv[i].div; i++) {\n" - "> > +\t\ttmp_prate =3D DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);\n" - "> > +\t\ttmp_rate =3D divider_round_rate(hw, rate, &tmp_prate, NULL,\n" + "> > +\tfor (i = 0; ac100_clkout_prediv[i].div; i++) {\n" + "> > +\t\ttmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);\n" + "> > +\t\ttmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,\n" "> > +\t\t\t\t\t AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +\n" "> > +\t\tif (tmp_rate > rate)\n" "> > +\t\t\tcontinue;\n" "> > +\t\tif (rate - tmp_rate < best_rate - tmp_rate)\n" - "> > +\t\t\tbest_rate =3D tmp_rate;\n" + "> > +\t\t\tbest_rate = tmp_rate;\n" "> > +\t}\n" "> > +\n" "> > +\treturn best_rate;\n" @@ -179,58 +168,56 @@ "> > +\t\t\t\t struct clk_rate_request *req)\n" "> > +{\n" "> > +\tstruct clk_hw *best_parent;\n" - "> > +\tunsigned long best =3D 0;\n" - "> > +\tint i, num_parents =3D clk_hw_get_num_parents(hw);\n" + "> > +\tunsigned long best = 0;\n" + "> > +\tint i, num_parents = clk_hw_get_num_parents(hw);\n" "> > +\n" - "> > +\tfor (i =3D 0; i < num_parents; i++) {\n" - "> > +\t\tstruct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i);\n" - "> > +\t\tunsigned long tmp, prate =3D clk_hw_get_rate(parent);\n" + "> > +\tfor (i = 0; i < num_parents; i++) {\n" + "> > +\t\tstruct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);\n" + "> > +\t\tunsigned long tmp, prate = clk_hw_get_rate(parent);\n" "> > +\n" - "> > +\t\ttmp =3D ac100_clkout_round_rate(hw, req->rate, prate);\n" + "> > +\t\ttmp = ac100_clkout_round_rate(hw, req->rate, prate);\n" "> > +\n" "> > +\t\tif (tmp > req->rate)\n" "> > +\t\t\tcontinue;\n" "> > +\t\tif (req->rate - tmp < req->rate - best) {\n" - "> > +\t\t\tbest =3D tmp;\n" - "> > +\t\t\tbest_parent =3D parent;\n" + "> > +\t\t\tbest = tmp;\n" + "> > +\t\t\tbest_parent = parent;\n" "> > +\t\t}\n" "> > +\t}\n" "> > +\n" "> > +\tif (!best)\n" "> > +\t\treturn -EINVAL;\n" "> > +\n" - "> > +\treq->best_parent_hw =3D best_parent;\n" - "> > +\treq->best_parent_rate =3D best;\n" - "> > +\treq->rate =3D best;\n" + "> > +\treq->best_parent_hw = best_parent;\n" + "> > +\treq->best_parent_rate = best;\n" + "> > +\treq->rate = best;\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" - "> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate=\n" - ",\n" + "> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,\n" "> > +\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" - "> > +\tint div =3D 0, pre_div =3D 0;\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" + "> > +\tint div = 0, pre_div = 0;\n" "> > +\n" "> > +\tdo {\n" - "> > +\t\tdiv =3D divider_get_val(rate * ac100_clkout_prediv[pre_div].div,\n" + "> > +\t\tdiv = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,\n" "> > +\t\t\t\t prate, NULL, AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" - "> > +\t\tif (div >=3D 0)\n" + "> > +\t\tif (div >= 0)\n" "> > +\t\t\tbreak;\n" - "> > +\t} while (prate !=3D AC100_RTC_32K_RATE &&\n" + "> > +\t} while (prate != AC100_RTC_32K_RATE &&\n" "> > +\t\t ac100_clkout_prediv[++pre_div].div);\n" "> > +\n" "> > +\tif (div < 0)\n" "> > +\t\treturn div;\n" "> > +\n" - "> > +\tpre_div =3D ac100_clkout_prediv[pre_div].val;\n" + "> > +\tpre_div = ac100_clkout_prediv[pre_div].val;\n" "> > +\n" "> > +\tregmap_update_bits(clk->regmap, clk->offset,\n" "> > +\t\t\t ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |\n" - "> > +\t\t\t ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_=\n" - "SHIFT,\n" + "> > +\t\t\t ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,\n" "> > +\t\t\t (div - 1) << AC100_CLKOUT_DIV_SHIFT |\n" "> > +\t\t\t (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);\n" "> > +\n" @@ -239,7 +226,7 @@ "> > +\n" "> > +static int ac100_clkout_prepare(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\treturn regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,\n" "> > +\t\t\t\t AC100_CLKOUT_EN);\n" @@ -247,14 +234,14 @@ "> > +\n" "> > +static void ac100_clkout_unprepare(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\tregmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);\n" "> > +}\n" "> > +\n" "> > +static int ac100_clkout_is_prepared(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" @@ -264,7 +251,7 @@ "> > +\n" "> > +static u8 ac100_clkout_get_parent(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" @@ -274,81 +261,80 @@ "> > +\n" "> > +static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\treturn regmap_update_bits(clk->regmap, clk->offset,\n" "> > +\t\t\t\t BIT(AC100_CLKOUT_MUX_SHIFT),\n" "> > +\t\t\t\t index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);\n" "> > +}\n" "> > +\n" - "> > +static const struct clk_ops ac100_clkout_ops =3D {\n" - "> > +\t.prepare\t=3D ac100_clkout_prepare,\n" - "> > +\t.unprepare\t=3D ac100_clkout_unprepare,\n" - "> > +\t.is_prepared\t=3D ac100_clkout_is_prepared,\n" - "> > +\t.recalc_rate\t=3D ac100_clkout_recalc_rate,\n" - "> > +\t.determine_rate\t=3D ac100_clkout_determine_rate,\n" - "> > +\t.get_parent\t=3D ac100_clkout_get_parent,\n" - "> > +\t.set_parent\t=3D ac100_clkout_set_parent,\n" - "> > +\t.set_rate\t=3D ac100_clkout_set_rate,\n" + "> > +static const struct clk_ops ac100_clkout_ops = {\n" + "> > +\t.prepare\t= ac100_clkout_prepare,\n" + "> > +\t.unprepare\t= ac100_clkout_unprepare,\n" + "> > +\t.is_prepared\t= ac100_clkout_is_prepared,\n" + "> > +\t.recalc_rate\t= ac100_clkout_recalc_rate,\n" + "> > +\t.determine_rate\t= ac100_clkout_determine_rate,\n" + "> > +\t.get_parent\t= ac100_clkout_get_parent,\n" + "> > +\t.set_parent\t= ac100_clkout_set_parent,\n" + "> > +\t.set_rate\t= ac100_clkout_set_rate,\n" "> > +};\n" "> > +\n" "> > +static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)\n" "> > +{\n" - "> > +\tstruct device_node *np =3D chip->dev->of_node;\n" - "> > +\tconst char *parents[2] =3D {AC100_RTC_32K_NAME};\n" + "> > +\tstruct device_node *np = chip->dev->of_node;\n" + "> > +\tconst char *parents[2] = {AC100_RTC_32K_NAME};\n" "> > +\tint i, ret;\n" "> > +\n" - "> > +\tchip->clk_data =3D devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +\n" + "> > +\tchip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +\n" "> > +\t\t\t\t\t\t sizeof(*chip->clk_data->hws) *\n" "> > +\t\t\t\t\t\t AC100_CLKOUT_NUM,\n" "> > +\t\t\t\t\t\t GFP_KERNEL);\n" "> > +\tif (!chip->clk_data)\n" "> > +\t\treturn -ENOMEM;\n" "> > +\n" - "> > +\tchip->rtc_32k_clk =3D clk_hw_register_fixed_rate(chip->dev,\n" + "> > +\tchip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,\n" "> > +\t\t\t\t\t\t AC100_RTC_32K_NAME,\n" "> > +\t\t\t\t\t\t NULL, 0,\n" "> > +\t\t\t\t\t\t AC100_RTC_32K_RATE);\n" "> > +\tif (IS_ERR(chip->rtc_32k_clk)) {\n" - "> > +\t\tret =3D PTR_ERR(chip->rtc_32k_clk);\n" + "> > +\t\tret = PTR_ERR(chip->rtc_32k_clk);\n" "> > +\t\tdev_err(chip->dev, \"Failed to register RTC-32k clock: %d\\n\",\n" "> > +\t\t\tret);\n" "> > +\t\treturn ret;\n" "> > +\t}\n" "> > +\n" - "> > +\tparents[1] =3D of_clk_get_parent_name(np, 0);\n" + "> > +\tparents[1] = of_clk_get_parent_name(np, 0);\n" "> > +\tif (!parents[1]) {\n" "> > +\t\tdev_err(chip->dev, \"Failed to get ADDA 4M clock\\n\");\n" "> > +\t\treturn -EINVAL;\n" "> > +\t}\n" "> > +\n" - "> > +\tfor (i =3D 0; i < AC100_CLKOUT_NUM; i++) {\n" - "> > +\t\tstruct ac100_clkout *clk =3D &chip->clks[i];\n" - "> > +\t\tstruct clk_init_data init =3D {\n" - "> > +\t\t\t.name =3D ac100_clkout_names[i],\n" - "> > +\t\t\t.ops =3D &ac100_clkout_ops,\n" - "> > +\t\t\t.parent_names =3D parents,\n" - "> > +\t\t\t.num_parents =3D ARRAY_SIZE(parents),\n" - "> > +\t\t\t.flags =3D 0,\n" + "> > +\tfor (i = 0; i < AC100_CLKOUT_NUM; i++) {\n" + "> > +\t\tstruct ac100_clkout *clk = &chip->clks[i];\n" + "> > +\t\tstruct clk_init_data init = {\n" + "> > +\t\t\t.name = ac100_clkout_names[i],\n" + "> > +\t\t\t.ops = &ac100_clkout_ops,\n" + "> > +\t\t\t.parent_names = parents,\n" + "> > +\t\t\t.num_parents = ARRAY_SIZE(parents),\n" + "> > +\t\t\t.flags = 0,\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tclk->regmap =3D chip->regmap;\n" - "> > +\t\tclk->offset =3D AC100_CLKOUT_CTRL1 + i;\n" - "> > +\t\tclk->hw.init =3D &init;\n" + "> > +\t\tclk->regmap = chip->regmap;\n" + "> > +\t\tclk->offset = AC100_CLKOUT_CTRL1 + i;\n" + "> > +\t\tclk->hw.init = &init;\n" "> > +\n" - "> > +\t\tret =3D devm_clk_hw_register(chip->dev, &clk->hw);\n" + "> > +\t\tret = devm_clk_hw_register(chip->dev, &clk->hw);\n" "> > +\t\tif (ret) {\n" "> > +\t\t\tdev_err(chip->dev, \"Failed to register clk '%s': %d\\n\",\n" "> > +\t\t\t\tinit.name, ret);\n" "> > +\t\t\tgoto err_unregister_rtc_32k;\n" "> > +\t\t}\n" "> > +\n" - "> > +\t\tchip->clk_data->hws[i] =3D &clk->hw;\n" + "> > +\t\tchip->clk_data->hws[i] = &clk->hw;\n" "> > +\t}\n" "> > +\n" - "> > +\tchip->clk_data->num =3D i;\n" - "> > +\tret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_d=\n" - "ata);\n" + "> > +\tchip->clk_data->num = i;\n" + "> > +\tret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);\n" "> > +\tif (ret)\n" "> > +\t\tgoto err_unregister_rtc_32k;\n" "> > +\n" @@ -369,62 +355,48 @@ "> > +/**\n" "> > + * RTC related bits\n" "> > + */\n" - "> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc=\n" - "_tm)\n" + "> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)\n" "> > {\n" - "> > \tstruct ac100_rtc_dev *chip =3D dev_get_drvdata(dev);\n" - "> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device=\n" - " *pdev)\n" + "> > \tstruct ac100_rtc_dev *chip = dev_get_drvdata(dev);\n" + "> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device *pdev)\n" "> > \t\treturn PTR_ERR(chip->rtc);\n" "> > \t}\n" - "> > =20\n" - "> > +\tret =3D ac100_rtc_register_clks(chip);\n" + "> > \n" + "> > +\tret = ac100_rtc_register_clks(chip);\n" "> > +\tif (ret)\n" "> > +\t\treturn ret;\n" "> > +\n" "> > \tdev_info(&pdev->dev, \"RTC enabled\\n\");\n" - "> > =20\n" + "> > \n" "> > \treturn 0;\n" "> > }\n" - "> > =20\n" + "> > \n" "> > +static int ac100_rtc_remove(struct platform_device *pdev)\n" "> > +{\n" - "> > +\tstruct ac100_rtc_dev *chip =3D platform_get_drvdata(pdev);\n" + "> > +\tstruct ac100_rtc_dev *chip = platform_get_drvdata(pdev);\n" "> > +\n" "> > +\tac100_rtc_unregister_clks(chip);\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" - "> > static const struct of_device_id ac100_rtc_match[] =3D {\n" - "> > \t{ .compatible =3D \"x-powers,ac100-rtc\" },\n" + "> > static const struct of_device_id ac100_rtc_match[] = {\n" + "> > \t{ .compatible = \"x-powers,ac100-rtc\" },\n" "> > \t{ },\n" "> > @@ -313,6 +614,7 @@ MODULE_DEVICE_TABLE(of, ac100_rtc_match);\n" - "> > =20\n" - "> > static struct platform_driver ac100_rtc_driver =3D {\n" - "> > \t.probe\t\t=3D ac100_rtc_probe,\n" - "> > +\t.remove\t\t=3D ac100_rtc_remove,\n" - "> > \t.driver\t\t=3D {\n" - "> > \t\t.name\t\t=3D \"ac100-rtc\",\n" - "> > \t\t.of_match_table\t=3D of_match_ptr(ac100_rtc_match),\n" - ">=20\n" + "> > \n" + "> > static struct platform_driver ac100_rtc_driver = {\n" + "> > \t.probe\t\t= ac100_rtc_probe,\n" + "> > +\t.remove\t\t= ac100_rtc_remove,\n" + "> > \t.driver\t\t= {\n" + "> > \t\t.name\t\t= \"ac100-rtc\",\n" + "> > \t\t.of_match_table\t= of_match_ptr(ac100_rtc_match),\n" + "> \n" "\n" - "--=20\n" + "-- \n" "Lee Jones\n" "Linaro STMicroelectronics Landing Team Lead\n" - "Linaro.org =E2=94=82 Open source software for ARM SoCs\n" - "Follow Linaro: Facebook | Twitter | Blog\n" - "\n" - "--=20\n" - "You received this message because you are subscribed to \"rtc-linux\".\n" - "Membership options at http://groups.google.com/group/rtc-linux .\n" - "Please read http://groups.google.com/group/rtc-linux/web/checklist\n" - "before submitting a driver.\n" - "---=20\n" - "You received this message because you are subscribed to the Google Groups \"=\n" - "rtc-linux\" group.\n" - "To unsubscribe from this group and stop receiving emails from it, send an e=\n" - "mail to rtc-linux+unsubscribe@googlegroups.com.\n" - For more options, visit https://groups.google.com/d/optout. + "Linaro.org ? Open source software for ARM SoCs\n" + Follow Linaro: Facebook | Twitter | Blog -ef9ae234c7069853050b709159a4cc410ba093e6b4d3e4c9fa41c93aace225c1 +66418515060ac3a9d0d9664cfe1ecf278ef9e99873e92d1dbeb291a3ddd67a81
diff --git a/a/1.txt b/N2/1.txt index 119d31b..99e74c6 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -4,27 +4,26 @@ On Fri, 08 Jul 2016, Alexandre Belloni wrote: > > The AC100's RTC side has 3 clock outputs on external pins, which can > > provide a clock signal to the SoC or other modules, such as WiFi or > > GSM modules. -> >=20 +> > > > Support this with a custom clk driver integrated with the rtc driver. -> >=20 -> > Signed-off-by: Chen-Yu Tsai <wens@csie.org> -> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> ->=20 +> > +> > Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> +> Acked-by: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> +> > > --- > > Changes since v4: none -> >=20 +> > > > Changes since v3: -> >=20 +> > > > - Renamed clk32k prefixes to clkout, except for the internal 32k clk > > - Changed default clk output names to "ac100-cko{1,2,3}-rtc" > > - Moved 4M ADDA clk to codec side -> >=20 +> > > > Changes since v2: none > > Changes since v1: none -> >=20 +> > > > --- -> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++= -++++++++ +> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 302 insertions(+) Applied, thanks. @@ -35,7 +34,7 @@ Applied, thanks. > > +++ b/drivers/rtc/rtc-ac100.c > > @@ -16,6 +16,7 @@ > > */ -> > =20 +> > > > #include <linux/bcd.h> > > +#include <linux/clk-provider.h> > > #include <linux/device.h> @@ -44,7 +43,7 @@ Applied, thanks. > > @@ -31,6 +32,15 @@ > > /* Control register */ > > #define AC100_RTC_CTRL_24HOUR BIT(0) -> > =20 +> > > > +/* Clock output register bits */ > > +#define AC100_CLKOUT_PRE_DIV_SHIFT 5 > > +#define AC100_CLKOUT_PRE_DIV_WIDTH 3 @@ -60,21 +59,20 @@ Applied, thanks. > > @@ -67,14 +77,292 @@ > > #define AC100_YEAR_MAX 2069 > > #define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900) -> > =20 +> > > > +struct ac100_clkout { > > + struct clk_hw hw; > > + struct regmap *regmap; > > + u8 offset; > > +}; > > + -> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw= -) +> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw) > > + > > +#define AC100_RTC_32K_NAME "ac100-rtc-32k" > > +#define AC100_RTC_32K_RATE 32768 > > +#define AC100_CLKOUT_NUM 3 > > + -> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] =3D { +> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = { > > + "ac100-cko1-rtc", > > + "ac100-cko2-rtc", > > + "ac100-cko3-rtc", @@ -91,69 +89,67 @@ Applied, thanks. > > + struct ac100_clkout clks[AC100_CLKOUT_NUM]; > > + struct clk_hw_onecell_data *clk_data; > > }; -> > =20 +> > > > +/** > > + * Clock controls for 3 clock output pins > > + */ > > + -> > +static const struct clk_div_table ac100_clkout_prediv[] =3D { -> > + { .val =3D 0, .div =3D 1 }, -> > + { .val =3D 1, .div =3D 2 }, -> > + { .val =3D 2, .div =3D 4 }, -> > + { .val =3D 3, .div =3D 8 }, -> > + { .val =3D 4, .div =3D 16 }, -> > + { .val =3D 5, .div =3D 32 }, -> > + { .val =3D 6, .div =3D 64 }, -> > + { .val =3D 7, .div =3D 122 }, +> > +static const struct clk_div_table ac100_clkout_prediv[] = { +> > + { .val = 0, .div = 1 }, +> > + { .val = 1, .div = 2 }, +> > + { .val = 2, .div = 4 }, +> > + { .val = 3, .div = 8 }, +> > + { .val = 4, .div = 16 }, +> > + { .val = 5, .div = 32 }, +> > + { .val = 6, .div = 64 }, +> > + { .val = 7, .div = 122 }, > > + { }, > > +}; > > + -> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz = -*/ +> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */ > > +static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw, > > + unsigned long prate) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg, div; > > + > > + regmap_read(clk->regmap, clk->offset, ®); > > + > > + /* Handle pre-divider first */ -> > + if (prate !=3D AC100_RTC_32K_RATE) { -> > + div =3D (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) & +> > + if (prate != AC100_RTC_32K_RATE) { +> > + div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) & > > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1); -> > + prate =3D divider_recalc_rate(hw, prate, div, +> > + prate = divider_recalc_rate(hw, prate, div, > > + ac100_clkout_prediv, 0); > > + } > > + -> > + div =3D (reg >> AC100_CLKOUT_DIV_SHIFT) & +> > + div = (reg >> AC100_CLKOUT_DIV_SHIFT) & > > + (BIT(AC100_CLKOUT_DIV_WIDTH) - 1); > > + return divider_recalc_rate(hw, prate, div, NULL, > > + CLK_DIVIDER_POWER_OF_TWO); > > +} > > + -> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long r= -ate, +> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long prate) > > +{ -> > + unsigned long best_rate =3D 0, tmp_rate, tmp_prate; +> > + unsigned long best_rate = 0, tmp_rate, tmp_prate; > > + int i; > > + -> > + if (prate =3D=3D AC100_RTC_32K_RATE) +> > + if (prate == AC100_RTC_32K_RATE) > > + return divider_round_rate(hw, rate, &prate, NULL, > > + AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); > > + -> > + for (i =3D 0; ac100_clkout_prediv[i].div; i++) { -> > + tmp_prate =3D DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); -> > + tmp_rate =3D divider_round_rate(hw, rate, &tmp_prate, NULL, +> > + for (i = 0; ac100_clkout_prediv[i].div; i++) { +> > + tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); +> > + tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL, > > + AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); > > + > > + if (tmp_rate > rate) > > + continue; > > + if (rate - tmp_rate < best_rate - tmp_rate) -> > + best_rate =3D tmp_rate; +> > + best_rate = tmp_rate; > > + } > > + > > + return best_rate; @@ -163,58 +159,56 @@ ate, > > + struct clk_rate_request *req) > > +{ > > + struct clk_hw *best_parent; -> > + unsigned long best =3D 0; -> > + int i, num_parents =3D clk_hw_get_num_parents(hw); +> > + unsigned long best = 0; +> > + int i, num_parents = clk_hw_get_num_parents(hw); > > + -> > + for (i =3D 0; i < num_parents; i++) { -> > + struct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i); -> > + unsigned long tmp, prate =3D clk_hw_get_rate(parent); +> > + for (i = 0; i < num_parents; i++) { +> > + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); +> > + unsigned long tmp, prate = clk_hw_get_rate(parent); > > + -> > + tmp =3D ac100_clkout_round_rate(hw, req->rate, prate); +> > + tmp = ac100_clkout_round_rate(hw, req->rate, prate); > > + > > + if (tmp > req->rate) > > + continue; > > + if (req->rate - tmp < req->rate - best) { -> > + best =3D tmp; -> > + best_parent =3D parent; +> > + best = tmp; +> > + best_parent = parent; > > + } > > + } > > + > > + if (!best) > > + return -EINVAL; > > + -> > + req->best_parent_hw =3D best_parent; -> > + req->best_parent_rate =3D best; -> > + req->rate =3D best; +> > + req->best_parent_hw = best_parent; +> > + req->best_parent_rate = best; +> > + req->rate = best; > > + > > + return 0; > > +} > > + -> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate= -, +> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long prate) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); -> > + int div =3D 0, pre_div =3D 0; +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); +> > + int div = 0, pre_div = 0; > > + > > + do { -> > + div =3D divider_get_val(rate * ac100_clkout_prediv[pre_div].div, +> > + div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div, > > + prate, NULL, AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); -> > + if (div >=3D 0) +> > + if (div >= 0) > > + break; -> > + } while (prate !=3D AC100_RTC_32K_RATE && +> > + } while (prate != AC100_RTC_32K_RATE && > > + ac100_clkout_prediv[++pre_div].div); > > + > > + if (div < 0) > > + return div; > > + -> > + pre_div =3D ac100_clkout_prediv[pre_div].val; +> > + pre_div = ac100_clkout_prediv[pre_div].val; > > + > > + regmap_update_bits(clk->regmap, clk->offset, > > + ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT | -> > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_= -SHIFT, +> > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT, > > + (div - 1) << AC100_CLKOUT_DIV_SHIFT | > > + (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT); > > + @@ -223,7 +217,7 @@ SHIFT, > > + > > +static int ac100_clkout_prepare(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, > > + AC100_CLKOUT_EN); @@ -231,14 +225,14 @@ SHIFT, > > + > > +static void ac100_clkout_unprepare(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0); > > +} > > + > > +static int ac100_clkout_is_prepared(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg; > > + > > + regmap_read(clk->regmap, clk->offset, ®); @@ -248,7 +242,7 @@ SHIFT, > > + > > +static u8 ac100_clkout_get_parent(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg; > > + > > + regmap_read(clk->regmap, clk->offset, ®); @@ -258,81 +252,80 @@ SHIFT, > > + > > +static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + return regmap_update_bits(clk->regmap, clk->offset, > > + BIT(AC100_CLKOUT_MUX_SHIFT), > > + index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0); > > +} > > + -> > +static const struct clk_ops ac100_clkout_ops =3D { -> > + .prepare =3D ac100_clkout_prepare, -> > + .unprepare =3D ac100_clkout_unprepare, -> > + .is_prepared =3D ac100_clkout_is_prepared, -> > + .recalc_rate =3D ac100_clkout_recalc_rate, -> > + .determine_rate =3D ac100_clkout_determine_rate, -> > + .get_parent =3D ac100_clkout_get_parent, -> > + .set_parent =3D ac100_clkout_set_parent, -> > + .set_rate =3D ac100_clkout_set_rate, +> > +static const struct clk_ops ac100_clkout_ops = { +> > + .prepare = ac100_clkout_prepare, +> > + .unprepare = ac100_clkout_unprepare, +> > + .is_prepared = ac100_clkout_is_prepared, +> > + .recalc_rate = ac100_clkout_recalc_rate, +> > + .determine_rate = ac100_clkout_determine_rate, +> > + .get_parent = ac100_clkout_get_parent, +> > + .set_parent = ac100_clkout_set_parent, +> > + .set_rate = ac100_clkout_set_rate, > > +}; > > + > > +static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip) > > +{ -> > + struct device_node *np =3D chip->dev->of_node; -> > + const char *parents[2] =3D {AC100_RTC_32K_NAME}; +> > + struct device_node *np = chip->dev->of_node; +> > + const char *parents[2] = {AC100_RTC_32K_NAME}; > > + int i, ret; > > + -> > + chip->clk_data =3D devm_kzalloc(chip->dev, sizeof(*chip->clk_data) + +> > + chip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) + > > + sizeof(*chip->clk_data->hws) * > > + AC100_CLKOUT_NUM, > > + GFP_KERNEL); > > + if (!chip->clk_data) > > + return -ENOMEM; > > + -> > + chip->rtc_32k_clk =3D clk_hw_register_fixed_rate(chip->dev, +> > + chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev, > > + AC100_RTC_32K_NAME, > > + NULL, 0, > > + AC100_RTC_32K_RATE); > > + if (IS_ERR(chip->rtc_32k_clk)) { -> > + ret =3D PTR_ERR(chip->rtc_32k_clk); +> > + ret = PTR_ERR(chip->rtc_32k_clk); > > + dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n", > > + ret); > > + return ret; > > + } > > + -> > + parents[1] =3D of_clk_get_parent_name(np, 0); +> > + parents[1] = of_clk_get_parent_name(np, 0); > > + if (!parents[1]) { > > + dev_err(chip->dev, "Failed to get ADDA 4M clock\n"); > > + return -EINVAL; > > + } > > + -> > + for (i =3D 0; i < AC100_CLKOUT_NUM; i++) { -> > + struct ac100_clkout *clk =3D &chip->clks[i]; -> > + struct clk_init_data init =3D { -> > + .name =3D ac100_clkout_names[i], -> > + .ops =3D &ac100_clkout_ops, -> > + .parent_names =3D parents, -> > + .num_parents =3D ARRAY_SIZE(parents), -> > + .flags =3D 0, +> > + for (i = 0; i < AC100_CLKOUT_NUM; i++) { +> > + struct ac100_clkout *clk = &chip->clks[i]; +> > + struct clk_init_data init = { +> > + .name = ac100_clkout_names[i], +> > + .ops = &ac100_clkout_ops, +> > + .parent_names = parents, +> > + .num_parents = ARRAY_SIZE(parents), +> > + .flags = 0, > > + }; > > + -> > + clk->regmap =3D chip->regmap; -> > + clk->offset =3D AC100_CLKOUT_CTRL1 + i; -> > + clk->hw.init =3D &init; +> > + clk->regmap = chip->regmap; +> > + clk->offset = AC100_CLKOUT_CTRL1 + i; +> > + clk->hw.init = &init; > > + -> > + ret =3D devm_clk_hw_register(chip->dev, &clk->hw); +> > + ret = devm_clk_hw_register(chip->dev, &clk->hw); > > + if (ret) { > > + dev_err(chip->dev, "Failed to register clk '%s': %d\n", > > + init.name, ret); > > + goto err_unregister_rtc_32k; > > + } > > + -> > + chip->clk_data->hws[i] =3D &clk->hw; +> > + chip->clk_data->hws[i] = &clk->hw; > > + } > > + -> > + chip->clk_data->num =3D i; -> > + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_d= -ata); +> > + chip->clk_data->num = i; +> > + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data); > > + if (ret) > > + goto err_unregister_rtc_32k; > > + @@ -353,60 +346,56 @@ ata); > > +/** > > + * RTC related bits > > + */ -> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc= -_tm) +> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm) > > { -> > struct ac100_rtc_dev *chip =3D dev_get_drvdata(dev); -> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device= - *pdev) +> > struct ac100_rtc_dev *chip = dev_get_drvdata(dev); +> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device *pdev) > > return PTR_ERR(chip->rtc); > > } -> > =20 -> > + ret =3D ac100_rtc_register_clks(chip); +> > +> > + ret = ac100_rtc_register_clks(chip); > > + if (ret) > > + return ret; > > + > > dev_info(&pdev->dev, "RTC enabled\n"); -> > =20 +> > > > return 0; > > } -> > =20 +> > > > +static int ac100_rtc_remove(struct platform_device *pdev) > > +{ -> > + struct ac100_rtc_dev *chip =3D platform_get_drvdata(pdev); +> > + struct ac100_rtc_dev *chip = platform_get_drvdata(pdev); > > + > > + ac100_rtc_unregister_clks(chip); > > + > > + return 0; > > +} > > + -> > static const struct of_device_id ac100_rtc_match[] =3D { -> > { .compatible =3D "x-powers,ac100-rtc" }, +> > static const struct of_device_id ac100_rtc_match[] = { +> > { .compatible = "x-powers,ac100-rtc" }, > > { }, > > @@ -313,6 +614,7 @@ MODULE_DEVICE_TABLE(of, ac100_rtc_match); -> > =20 -> > static struct platform_driver ac100_rtc_driver =3D { -> > .probe =3D ac100_rtc_probe, -> > + .remove =3D ac100_rtc_remove, -> > .driver =3D { -> > .name =3D "ac100-rtc", -> > .of_match_table =3D of_match_ptr(ac100_rtc_match), ->=20 +> > +> > static struct platform_driver ac100_rtc_driver = { +> > .probe = ac100_rtc_probe, +> > + .remove = ac100_rtc_remove, +> > .driver = { +> > .name = "ac100-rtc", +> > .of_match_table = of_match_ptr(ac100_rtc_match), +> ---=20 +-- Lee Jones Linaro STMicroelectronics Landing Team Lead -Linaro.org =E2=94=82 Open source software for ARM SoCs +Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog ---=20 +-- You received this message because you are subscribed to "rtc-linux". Membership options at http://groups.google.com/group/rtc-linux . Please read http://groups.google.com/group/rtc-linux/web/checklist before submitting a driver. ----=20 -You received this message because you are subscribed to the Google Groups "= -rtc-linux" group. -To unsubscribe from this group and stop receiving emails from it, send an e= -mail to rtc-linux+unsubscribe@googlegroups.com. +--- +You received this message because you are subscribed to the Google Groups "rtc-linux" group. +To unsubscribe from this group and stop receiving emails from it, send an email to rtc-linux+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. diff --git a/a/content_digest b/N2/content_digest index a5539bb..0e6c2fe 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,17 +1,18 @@ "ref\01467988422-17934-1-git-send-email-wens@csie.org\0" "ref\01467988422-17934-5-git-send-email-wens@csie.org\0" "ref\020160708162932.GN22202@piout.net\0" - "From\0Lee Jones <lee.jones@linaro.org>\0" - "Subject\0[rtc-linux] Re: [PATCH v5 4/7] rtc: ac100: Add clk output support\0" + "ref\020160708162932.GN22202-m++hUPXGwpdeoWH0uzbU5w@public.gmane.org\0" + "From\0Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" + "Subject\0Re: [PATCH v5 4/7] rtc: ac100: Add clk output support\0" "Date\0Mon, 8 Aug 2016 12:56:51 +0100\0" - "To\0Alexandre Belloni <alexandre.belloni@free-electrons.com>\0" - "Cc\0Chen-Yu Tsai <wens@csie.org>" - Alessandro Zummo <a.zummo@towertech.it> - Maxime Ripard <maxime.ripard@free-electrons.com> - linux-kernel@vger.kernel.org - rtc-linux@googlegroups.com - devicetree@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Cc\0Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>" + Alessandro Zummo <a.zummo-BfzFCNDTiLLj+vYz1yj4TQ@public.gmane.org> + Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + rtc-linux-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "On Fri, 08 Jul 2016, Alexandre Belloni wrote:\n" @@ -20,27 +21,26 @@ "> > The AC100's RTC side has 3 clock outputs on external pins, which can\n" "> > provide a clock signal to the SoC or other modules, such as WiFi or\n" "> > GSM modules.\n" - "> >=20\n" + "> > \n" "> > Support this with a custom clk driver integrated with the rtc driver.\n" - "> >=20\n" - "> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>\n" - "> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>\n" - ">=20\n" + "> > \n" + "> > Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>\n" + "> Acked-by: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\n" + "> \n" "> > ---\n" "> > Changes since v4: none\n" - "> >=20\n" + "> > \n" "> > Changes since v3:\n" - "> >=20\n" + "> > \n" "> > - Renamed clk32k prefixes to clkout, except for the internal 32k clk\n" "> > - Changed default clk output names to \"ac100-cko{1,2,3}-rtc\"\n" "> > - Moved 4M ADDA clk to codec side\n" - "> >=20\n" + "> > \n" "> > Changes since v2: none\n" "> > Changes since v1: none\n" - "> >=20\n" + "> > \n" "> > ---\n" - "> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++=\n" - "++++++++\n" + "> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++++\n" "> > 1 file changed, 302 insertions(+)\n" "\n" "Applied, thanks.\n" @@ -51,7 +51,7 @@ "> > +++ b/drivers/rtc/rtc-ac100.c\n" "> > @@ -16,6 +16,7 @@\n" "> > */\n" - "> > =20\n" + "> > \n" "> > #include <linux/bcd.h>\n" "> > +#include <linux/clk-provider.h>\n" "> > #include <linux/device.h>\n" @@ -60,7 +60,7 @@ "> > @@ -31,6 +32,15 @@\n" "> > /* Control register */\n" "> > #define AC100_RTC_CTRL_24HOUR\tBIT(0)\n" - "> > =20\n" + "> > \n" "> > +/* Clock output register bits */\n" "> > +#define AC100_CLKOUT_PRE_DIV_SHIFT\t5\n" "> > +#define AC100_CLKOUT_PRE_DIV_WIDTH\t3\n" @@ -76,21 +76,20 @@ "> > @@ -67,14 +77,292 @@\n" "> > #define AC100_YEAR_MAX\t\t\t\t2069\n" "> > #define AC100_YEAR_OFF\t\t\t\t(AC100_YEAR_MIN - 1900)\n" - "> > =20\n" + "> > \n" "> > +struct ac100_clkout {\n" "> > +\tstruct clk_hw hw;\n" "> > +\tstruct regmap *regmap;\n" "> > +\tu8 offset;\n" "> > +};\n" "> > +\n" - "> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw=\n" - ")\n" + "> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)\n" "> > +\n" "> > +#define AC100_RTC_32K_NAME\t\"ac100-rtc-32k\"\n" "> > +#define AC100_RTC_32K_RATE\t32768\n" "> > +#define AC100_CLKOUT_NUM\t3\n" "> > +\n" - "> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] =3D {\n" + "> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {\n" "> > +\t\"ac100-cko1-rtc\",\n" "> > +\t\"ac100-cko2-rtc\",\n" "> > +\t\"ac100-cko3-rtc\",\n" @@ -107,69 +106,67 @@ "> > +\tstruct ac100_clkout clks[AC100_CLKOUT_NUM];\n" "> > +\tstruct clk_hw_onecell_data *clk_data;\n" "> > };\n" - "> > =20\n" + "> > \n" "> > +/**\n" "> > + * Clock controls for 3 clock output pins\n" "> > + */\n" "> > +\n" - "> > +static const struct clk_div_table ac100_clkout_prediv[] =3D {\n" - "> > +\t{ .val =3D 0, .div =3D 1 },\n" - "> > +\t{ .val =3D 1, .div =3D 2 },\n" - "> > +\t{ .val =3D 2, .div =3D 4 },\n" - "> > +\t{ .val =3D 3, .div =3D 8 },\n" - "> > +\t{ .val =3D 4, .div =3D 16 },\n" - "> > +\t{ .val =3D 5, .div =3D 32 },\n" - "> > +\t{ .val =3D 6, .div =3D 64 },\n" - "> > +\t{ .val =3D 7, .div =3D 122 },\n" + "> > +static const struct clk_div_table ac100_clkout_prediv[] = {\n" + "> > +\t{ .val = 0, .div = 1 },\n" + "> > +\t{ .val = 1, .div = 2 },\n" + "> > +\t{ .val = 2, .div = 4 },\n" + "> > +\t{ .val = 3, .div = 8 },\n" + "> > +\t{ .val = 4, .div = 16 },\n" + "> > +\t{ .val = 5, .div = 32 },\n" + "> > +\t{ .val = 6, .div = 64 },\n" + "> > +\t{ .val = 7, .div = 122 },\n" "> > +\t{ },\n" "> > +};\n" "> > +\n" - "> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz =\n" - "*/\n" + "> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */\n" "> > +static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,\n" "> > +\t\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg, div;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" "> > +\n" "> > +\t/* Handle pre-divider first */\n" - "> > +\tif (prate !=3D AC100_RTC_32K_RATE) {\n" - "> > +\t\tdiv =3D (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &\n" + "> > +\tif (prate != AC100_RTC_32K_RATE) {\n" + "> > +\t\tdiv = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &\n" "> > +\t\t\t((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);\n" - "> > +\t\tprate =3D divider_recalc_rate(hw, prate, div,\n" + "> > +\t\tprate = divider_recalc_rate(hw, prate, div,\n" "> > +\t\t\t\t\t ac100_clkout_prediv, 0);\n" "> > +\t}\n" "> > +\n" - "> > +\tdiv =3D (reg >> AC100_CLKOUT_DIV_SHIFT) &\n" + "> > +\tdiv = (reg >> AC100_CLKOUT_DIV_SHIFT) &\n" "> > +\t\t(BIT(AC100_CLKOUT_DIV_WIDTH) - 1);\n" "> > +\treturn divider_recalc_rate(hw, prate, div, NULL,\n" "> > +\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +}\n" "> > +\n" - "> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long r=\n" - "ate,\n" + "> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,\n" "> > +\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tunsigned long best_rate =3D 0, tmp_rate, tmp_prate;\n" + "> > +\tunsigned long best_rate = 0, tmp_rate, tmp_prate;\n" "> > +\tint i;\n" "> > +\n" - "> > +\tif (prate =3D=3D AC100_RTC_32K_RATE)\n" + "> > +\tif (prate == AC100_RTC_32K_RATE)\n" "> > +\t\treturn divider_round_rate(hw, rate, &prate, NULL,\n" "> > +\t\t\t\t\t AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +\n" - "> > +\tfor (i =3D 0; ac100_clkout_prediv[i].div; i++) {\n" - "> > +\t\ttmp_prate =3D DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);\n" - "> > +\t\ttmp_rate =3D divider_round_rate(hw, rate, &tmp_prate, NULL,\n" + "> > +\tfor (i = 0; ac100_clkout_prediv[i].div; i++) {\n" + "> > +\t\ttmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);\n" + "> > +\t\ttmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,\n" "> > +\t\t\t\t\t AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +\n" "> > +\t\tif (tmp_rate > rate)\n" "> > +\t\t\tcontinue;\n" "> > +\t\tif (rate - tmp_rate < best_rate - tmp_rate)\n" - "> > +\t\t\tbest_rate =3D tmp_rate;\n" + "> > +\t\t\tbest_rate = tmp_rate;\n" "> > +\t}\n" "> > +\n" "> > +\treturn best_rate;\n" @@ -179,58 +176,56 @@ "> > +\t\t\t\t struct clk_rate_request *req)\n" "> > +{\n" "> > +\tstruct clk_hw *best_parent;\n" - "> > +\tunsigned long best =3D 0;\n" - "> > +\tint i, num_parents =3D clk_hw_get_num_parents(hw);\n" + "> > +\tunsigned long best = 0;\n" + "> > +\tint i, num_parents = clk_hw_get_num_parents(hw);\n" "> > +\n" - "> > +\tfor (i =3D 0; i < num_parents; i++) {\n" - "> > +\t\tstruct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i);\n" - "> > +\t\tunsigned long tmp, prate =3D clk_hw_get_rate(parent);\n" + "> > +\tfor (i = 0; i < num_parents; i++) {\n" + "> > +\t\tstruct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);\n" + "> > +\t\tunsigned long tmp, prate = clk_hw_get_rate(parent);\n" "> > +\n" - "> > +\t\ttmp =3D ac100_clkout_round_rate(hw, req->rate, prate);\n" + "> > +\t\ttmp = ac100_clkout_round_rate(hw, req->rate, prate);\n" "> > +\n" "> > +\t\tif (tmp > req->rate)\n" "> > +\t\t\tcontinue;\n" "> > +\t\tif (req->rate - tmp < req->rate - best) {\n" - "> > +\t\t\tbest =3D tmp;\n" - "> > +\t\t\tbest_parent =3D parent;\n" + "> > +\t\t\tbest = tmp;\n" + "> > +\t\t\tbest_parent = parent;\n" "> > +\t\t}\n" "> > +\t}\n" "> > +\n" "> > +\tif (!best)\n" "> > +\t\treturn -EINVAL;\n" "> > +\n" - "> > +\treq->best_parent_hw =3D best_parent;\n" - "> > +\treq->best_parent_rate =3D best;\n" - "> > +\treq->rate =3D best;\n" + "> > +\treq->best_parent_hw = best_parent;\n" + "> > +\treq->best_parent_rate = best;\n" + "> > +\treq->rate = best;\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" - "> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate=\n" - ",\n" + "> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,\n" "> > +\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" - "> > +\tint div =3D 0, pre_div =3D 0;\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" + "> > +\tint div = 0, pre_div = 0;\n" "> > +\n" "> > +\tdo {\n" - "> > +\t\tdiv =3D divider_get_val(rate * ac100_clkout_prediv[pre_div].div,\n" + "> > +\t\tdiv = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,\n" "> > +\t\t\t\t prate, NULL, AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" - "> > +\t\tif (div >=3D 0)\n" + "> > +\t\tif (div >= 0)\n" "> > +\t\t\tbreak;\n" - "> > +\t} while (prate !=3D AC100_RTC_32K_RATE &&\n" + "> > +\t} while (prate != AC100_RTC_32K_RATE &&\n" "> > +\t\t ac100_clkout_prediv[++pre_div].div);\n" "> > +\n" "> > +\tif (div < 0)\n" "> > +\t\treturn div;\n" "> > +\n" - "> > +\tpre_div =3D ac100_clkout_prediv[pre_div].val;\n" + "> > +\tpre_div = ac100_clkout_prediv[pre_div].val;\n" "> > +\n" "> > +\tregmap_update_bits(clk->regmap, clk->offset,\n" "> > +\t\t\t ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |\n" - "> > +\t\t\t ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_=\n" - "SHIFT,\n" + "> > +\t\t\t ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,\n" "> > +\t\t\t (div - 1) << AC100_CLKOUT_DIV_SHIFT |\n" "> > +\t\t\t (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);\n" "> > +\n" @@ -239,7 +234,7 @@ "> > +\n" "> > +static int ac100_clkout_prepare(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\treturn regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,\n" "> > +\t\t\t\t AC100_CLKOUT_EN);\n" @@ -247,14 +242,14 @@ "> > +\n" "> > +static void ac100_clkout_unprepare(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\tregmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);\n" "> > +}\n" "> > +\n" "> > +static int ac100_clkout_is_prepared(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" @@ -264,7 +259,7 @@ "> > +\n" "> > +static u8 ac100_clkout_get_parent(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" @@ -274,81 +269,80 @@ "> > +\n" "> > +static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\treturn regmap_update_bits(clk->regmap, clk->offset,\n" "> > +\t\t\t\t BIT(AC100_CLKOUT_MUX_SHIFT),\n" "> > +\t\t\t\t index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);\n" "> > +}\n" "> > +\n" - "> > +static const struct clk_ops ac100_clkout_ops =3D {\n" - "> > +\t.prepare\t=3D ac100_clkout_prepare,\n" - "> > +\t.unprepare\t=3D ac100_clkout_unprepare,\n" - "> > +\t.is_prepared\t=3D ac100_clkout_is_prepared,\n" - "> > +\t.recalc_rate\t=3D ac100_clkout_recalc_rate,\n" - "> > +\t.determine_rate\t=3D ac100_clkout_determine_rate,\n" - "> > +\t.get_parent\t=3D ac100_clkout_get_parent,\n" - "> > +\t.set_parent\t=3D ac100_clkout_set_parent,\n" - "> > +\t.set_rate\t=3D ac100_clkout_set_rate,\n" + "> > +static const struct clk_ops ac100_clkout_ops = {\n" + "> > +\t.prepare\t= ac100_clkout_prepare,\n" + "> > +\t.unprepare\t= ac100_clkout_unprepare,\n" + "> > +\t.is_prepared\t= ac100_clkout_is_prepared,\n" + "> > +\t.recalc_rate\t= ac100_clkout_recalc_rate,\n" + "> > +\t.determine_rate\t= ac100_clkout_determine_rate,\n" + "> > +\t.get_parent\t= ac100_clkout_get_parent,\n" + "> > +\t.set_parent\t= ac100_clkout_set_parent,\n" + "> > +\t.set_rate\t= ac100_clkout_set_rate,\n" "> > +};\n" "> > +\n" "> > +static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)\n" "> > +{\n" - "> > +\tstruct device_node *np =3D chip->dev->of_node;\n" - "> > +\tconst char *parents[2] =3D {AC100_RTC_32K_NAME};\n" + "> > +\tstruct device_node *np = chip->dev->of_node;\n" + "> > +\tconst char *parents[2] = {AC100_RTC_32K_NAME};\n" "> > +\tint i, ret;\n" "> > +\n" - "> > +\tchip->clk_data =3D devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +\n" + "> > +\tchip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +\n" "> > +\t\t\t\t\t\t sizeof(*chip->clk_data->hws) *\n" "> > +\t\t\t\t\t\t AC100_CLKOUT_NUM,\n" "> > +\t\t\t\t\t\t GFP_KERNEL);\n" "> > +\tif (!chip->clk_data)\n" "> > +\t\treturn -ENOMEM;\n" "> > +\n" - "> > +\tchip->rtc_32k_clk =3D clk_hw_register_fixed_rate(chip->dev,\n" + "> > +\tchip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,\n" "> > +\t\t\t\t\t\t AC100_RTC_32K_NAME,\n" "> > +\t\t\t\t\t\t NULL, 0,\n" "> > +\t\t\t\t\t\t AC100_RTC_32K_RATE);\n" "> > +\tif (IS_ERR(chip->rtc_32k_clk)) {\n" - "> > +\t\tret =3D PTR_ERR(chip->rtc_32k_clk);\n" + "> > +\t\tret = PTR_ERR(chip->rtc_32k_clk);\n" "> > +\t\tdev_err(chip->dev, \"Failed to register RTC-32k clock: %d\\n\",\n" "> > +\t\t\tret);\n" "> > +\t\treturn ret;\n" "> > +\t}\n" "> > +\n" - "> > +\tparents[1] =3D of_clk_get_parent_name(np, 0);\n" + "> > +\tparents[1] = of_clk_get_parent_name(np, 0);\n" "> > +\tif (!parents[1]) {\n" "> > +\t\tdev_err(chip->dev, \"Failed to get ADDA 4M clock\\n\");\n" "> > +\t\treturn -EINVAL;\n" "> > +\t}\n" "> > +\n" - "> > +\tfor (i =3D 0; i < AC100_CLKOUT_NUM; i++) {\n" - "> > +\t\tstruct ac100_clkout *clk =3D &chip->clks[i];\n" - "> > +\t\tstruct clk_init_data init =3D {\n" - "> > +\t\t\t.name =3D ac100_clkout_names[i],\n" - "> > +\t\t\t.ops =3D &ac100_clkout_ops,\n" - "> > +\t\t\t.parent_names =3D parents,\n" - "> > +\t\t\t.num_parents =3D ARRAY_SIZE(parents),\n" - "> > +\t\t\t.flags =3D 0,\n" + "> > +\tfor (i = 0; i < AC100_CLKOUT_NUM; i++) {\n" + "> > +\t\tstruct ac100_clkout *clk = &chip->clks[i];\n" + "> > +\t\tstruct clk_init_data init = {\n" + "> > +\t\t\t.name = ac100_clkout_names[i],\n" + "> > +\t\t\t.ops = &ac100_clkout_ops,\n" + "> > +\t\t\t.parent_names = parents,\n" + "> > +\t\t\t.num_parents = ARRAY_SIZE(parents),\n" + "> > +\t\t\t.flags = 0,\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tclk->regmap =3D chip->regmap;\n" - "> > +\t\tclk->offset =3D AC100_CLKOUT_CTRL1 + i;\n" - "> > +\t\tclk->hw.init =3D &init;\n" + "> > +\t\tclk->regmap = chip->regmap;\n" + "> > +\t\tclk->offset = AC100_CLKOUT_CTRL1 + i;\n" + "> > +\t\tclk->hw.init = &init;\n" "> > +\n" - "> > +\t\tret =3D devm_clk_hw_register(chip->dev, &clk->hw);\n" + "> > +\t\tret = devm_clk_hw_register(chip->dev, &clk->hw);\n" "> > +\t\tif (ret) {\n" "> > +\t\t\tdev_err(chip->dev, \"Failed to register clk '%s': %d\\n\",\n" "> > +\t\t\t\tinit.name, ret);\n" "> > +\t\t\tgoto err_unregister_rtc_32k;\n" "> > +\t\t}\n" "> > +\n" - "> > +\t\tchip->clk_data->hws[i] =3D &clk->hw;\n" + "> > +\t\tchip->clk_data->hws[i] = &clk->hw;\n" "> > +\t}\n" "> > +\n" - "> > +\tchip->clk_data->num =3D i;\n" - "> > +\tret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_d=\n" - "ata);\n" + "> > +\tchip->clk_data->num = i;\n" + "> > +\tret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);\n" "> > +\tif (ret)\n" "> > +\t\tgoto err_unregister_rtc_32k;\n" "> > +\n" @@ -369,62 +363,58 @@ "> > +/**\n" "> > + * RTC related bits\n" "> > + */\n" - "> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc=\n" - "_tm)\n" + "> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)\n" "> > {\n" - "> > \tstruct ac100_rtc_dev *chip =3D dev_get_drvdata(dev);\n" - "> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device=\n" - " *pdev)\n" + "> > \tstruct ac100_rtc_dev *chip = dev_get_drvdata(dev);\n" + "> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device *pdev)\n" "> > \t\treturn PTR_ERR(chip->rtc);\n" "> > \t}\n" - "> > =20\n" - "> > +\tret =3D ac100_rtc_register_clks(chip);\n" + "> > \n" + "> > +\tret = ac100_rtc_register_clks(chip);\n" "> > +\tif (ret)\n" "> > +\t\treturn ret;\n" "> > +\n" "> > \tdev_info(&pdev->dev, \"RTC enabled\\n\");\n" - "> > =20\n" + "> > \n" "> > \treturn 0;\n" "> > }\n" - "> > =20\n" + "> > \n" "> > +static int ac100_rtc_remove(struct platform_device *pdev)\n" "> > +{\n" - "> > +\tstruct ac100_rtc_dev *chip =3D platform_get_drvdata(pdev);\n" + "> > +\tstruct ac100_rtc_dev *chip = platform_get_drvdata(pdev);\n" "> > +\n" "> > +\tac100_rtc_unregister_clks(chip);\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" - "> > static const struct of_device_id ac100_rtc_match[] =3D {\n" - "> > \t{ .compatible =3D \"x-powers,ac100-rtc\" },\n" + "> > static const struct of_device_id ac100_rtc_match[] = {\n" + "> > \t{ .compatible = \"x-powers,ac100-rtc\" },\n" "> > \t{ },\n" "> > @@ -313,6 +614,7 @@ MODULE_DEVICE_TABLE(of, ac100_rtc_match);\n" - "> > =20\n" - "> > static struct platform_driver ac100_rtc_driver =3D {\n" - "> > \t.probe\t\t=3D ac100_rtc_probe,\n" - "> > +\t.remove\t\t=3D ac100_rtc_remove,\n" - "> > \t.driver\t\t=3D {\n" - "> > \t\t.name\t\t=3D \"ac100-rtc\",\n" - "> > \t\t.of_match_table\t=3D of_match_ptr(ac100_rtc_match),\n" - ">=20\n" + "> > \n" + "> > static struct platform_driver ac100_rtc_driver = {\n" + "> > \t.probe\t\t= ac100_rtc_probe,\n" + "> > +\t.remove\t\t= ac100_rtc_remove,\n" + "> > \t.driver\t\t= {\n" + "> > \t\t.name\t\t= \"ac100-rtc\",\n" + "> > \t\t.of_match_table\t= of_match_ptr(ac100_rtc_match),\n" + "> \n" "\n" - "--=20\n" + "-- \n" "Lee Jones\n" "Linaro STMicroelectronics Landing Team Lead\n" - "Linaro.org =E2=94=82 Open source software for ARM SoCs\n" + "Linaro.org \342\224\202 Open source software for ARM SoCs\n" "Follow Linaro: Facebook | Twitter | Blog\n" "\n" - "--=20\n" + "-- \n" "You received this message because you are subscribed to \"rtc-linux\".\n" "Membership options at http://groups.google.com/group/rtc-linux .\n" "Please read http://groups.google.com/group/rtc-linux/web/checklist\n" "before submitting a driver.\n" - "---=20\n" - "You received this message because you are subscribed to the Google Groups \"=\n" - "rtc-linux\" group.\n" - "To unsubscribe from this group and stop receiving emails from it, send an e=\n" - "mail to rtc-linux+unsubscribe@googlegroups.com.\n" + "--- \n" + "You received this message because you are subscribed to the Google Groups \"rtc-linux\" group.\n" + "To unsubscribe from this group and stop receiving emails from it, send an email to rtc-linux+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org\n" For more options, visit https://groups.google.com/d/optout. -ef9ae234c7069853050b709159a4cc410ba093e6b4d3e4c9fa41c93aace225c1 +a4a6d96bc4281f256dbbb0037291e7d08675824a6c893e0d8779e1dd8ef072e6
diff --git a/a/1.txt b/N3/1.txt index 119d31b..f244097 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -4,27 +4,26 @@ On Fri, 08 Jul 2016, Alexandre Belloni wrote: > > The AC100's RTC side has 3 clock outputs on external pins, which can > > provide a clock signal to the SoC or other modules, such as WiFi or > > GSM modules. -> >=20 +> > > > Support this with a custom clk driver integrated with the rtc driver. -> >=20 +> > > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> ->=20 +> > > --- > > Changes since v4: none -> >=20 +> > > > Changes since v3: -> >=20 +> > > > - Renamed clk32k prefixes to clkout, except for the internal 32k clk > > - Changed default clk output names to "ac100-cko{1,2,3}-rtc" > > - Moved 4M ADDA clk to codec side -> >=20 +> > > > Changes since v2: none > > Changes since v1: none -> >=20 +> > > > --- -> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++= -++++++++ +> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 302 insertions(+) Applied, thanks. @@ -35,7 +34,7 @@ Applied, thanks. > > +++ b/drivers/rtc/rtc-ac100.c > > @@ -16,6 +16,7 @@ > > */ -> > =20 +> > > > #include <linux/bcd.h> > > +#include <linux/clk-provider.h> > > #include <linux/device.h> @@ -44,7 +43,7 @@ Applied, thanks. > > @@ -31,6 +32,15 @@ > > /* Control register */ > > #define AC100_RTC_CTRL_24HOUR BIT(0) -> > =20 +> > > > +/* Clock output register bits */ > > +#define AC100_CLKOUT_PRE_DIV_SHIFT 5 > > +#define AC100_CLKOUT_PRE_DIV_WIDTH 3 @@ -60,21 +59,20 @@ Applied, thanks. > > @@ -67,14 +77,292 @@ > > #define AC100_YEAR_MAX 2069 > > #define AC100_YEAR_OFF (AC100_YEAR_MIN - 1900) -> > =20 +> > > > +struct ac100_clkout { > > + struct clk_hw hw; > > + struct regmap *regmap; > > + u8 offset; > > +}; > > + -> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw= -) +> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw) > > + > > +#define AC100_RTC_32K_NAME "ac100-rtc-32k" > > +#define AC100_RTC_32K_RATE 32768 > > +#define AC100_CLKOUT_NUM 3 > > + -> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] =3D { +> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = { > > + "ac100-cko1-rtc", > > + "ac100-cko2-rtc", > > + "ac100-cko3-rtc", @@ -91,69 +89,67 @@ Applied, thanks. > > + struct ac100_clkout clks[AC100_CLKOUT_NUM]; > > + struct clk_hw_onecell_data *clk_data; > > }; -> > =20 +> > > > +/** > > + * Clock controls for 3 clock output pins > > + */ > > + -> > +static const struct clk_div_table ac100_clkout_prediv[] =3D { -> > + { .val =3D 0, .div =3D 1 }, -> > + { .val =3D 1, .div =3D 2 }, -> > + { .val =3D 2, .div =3D 4 }, -> > + { .val =3D 3, .div =3D 8 }, -> > + { .val =3D 4, .div =3D 16 }, -> > + { .val =3D 5, .div =3D 32 }, -> > + { .val =3D 6, .div =3D 64 }, -> > + { .val =3D 7, .div =3D 122 }, +> > +static const struct clk_div_table ac100_clkout_prediv[] = { +> > + { .val = 0, .div = 1 }, +> > + { .val = 1, .div = 2 }, +> > + { .val = 2, .div = 4 }, +> > + { .val = 3, .div = 8 }, +> > + { .val = 4, .div = 16 }, +> > + { .val = 5, .div = 32 }, +> > + { .val = 6, .div = 64 }, +> > + { .val = 7, .div = 122 }, > > + { }, > > +}; > > + -> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz = -*/ +> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */ > > +static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw, > > + unsigned long prate) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg, div; > > + > > + regmap_read(clk->regmap, clk->offset, ®); > > + > > + /* Handle pre-divider first */ -> > + if (prate !=3D AC100_RTC_32K_RATE) { -> > + div =3D (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) & +> > + if (prate != AC100_RTC_32K_RATE) { +> > + div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) & > > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1); -> > + prate =3D divider_recalc_rate(hw, prate, div, +> > + prate = divider_recalc_rate(hw, prate, div, > > + ac100_clkout_prediv, 0); > > + } > > + -> > + div =3D (reg >> AC100_CLKOUT_DIV_SHIFT) & +> > + div = (reg >> AC100_CLKOUT_DIV_SHIFT) & > > + (BIT(AC100_CLKOUT_DIV_WIDTH) - 1); > > + return divider_recalc_rate(hw, prate, div, NULL, > > + CLK_DIVIDER_POWER_OF_TWO); > > +} > > + -> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long r= -ate, +> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long prate) > > +{ -> > + unsigned long best_rate =3D 0, tmp_rate, tmp_prate; +> > + unsigned long best_rate = 0, tmp_rate, tmp_prate; > > + int i; > > + -> > + if (prate =3D=3D AC100_RTC_32K_RATE) +> > + if (prate == AC100_RTC_32K_RATE) > > + return divider_round_rate(hw, rate, &prate, NULL, > > + AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); > > + -> > + for (i =3D 0; ac100_clkout_prediv[i].div; i++) { -> > + tmp_prate =3D DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); -> > + tmp_rate =3D divider_round_rate(hw, rate, &tmp_prate, NULL, +> > + for (i = 0; ac100_clkout_prediv[i].div; i++) { +> > + tmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val); +> > + tmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL, > > + AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); > > + > > + if (tmp_rate > rate) > > + continue; > > + if (rate - tmp_rate < best_rate - tmp_rate) -> > + best_rate =3D tmp_rate; +> > + best_rate = tmp_rate; > > + } > > + > > + return best_rate; @@ -163,58 +159,56 @@ ate, > > + struct clk_rate_request *req) > > +{ > > + struct clk_hw *best_parent; -> > + unsigned long best =3D 0; -> > + int i, num_parents =3D clk_hw_get_num_parents(hw); +> > + unsigned long best = 0; +> > + int i, num_parents = clk_hw_get_num_parents(hw); > > + -> > + for (i =3D 0; i < num_parents; i++) { -> > + struct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i); -> > + unsigned long tmp, prate =3D clk_hw_get_rate(parent); +> > + for (i = 0; i < num_parents; i++) { +> > + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i); +> > + unsigned long tmp, prate = clk_hw_get_rate(parent); > > + -> > + tmp =3D ac100_clkout_round_rate(hw, req->rate, prate); +> > + tmp = ac100_clkout_round_rate(hw, req->rate, prate); > > + > > + if (tmp > req->rate) > > + continue; > > + if (req->rate - tmp < req->rate - best) { -> > + best =3D tmp; -> > + best_parent =3D parent; +> > + best = tmp; +> > + best_parent = parent; > > + } > > + } > > + > > + if (!best) > > + return -EINVAL; > > + -> > + req->best_parent_hw =3D best_parent; -> > + req->best_parent_rate =3D best; -> > + req->rate =3D best; +> > + req->best_parent_hw = best_parent; +> > + req->best_parent_rate = best; +> > + req->rate = best; > > + > > + return 0; > > +} > > + -> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate= -, +> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long prate) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); -> > + int div =3D 0, pre_div =3D 0; +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); +> > + int div = 0, pre_div = 0; > > + > > + do { -> > + div =3D divider_get_val(rate * ac100_clkout_prediv[pre_div].div, +> > + div = divider_get_val(rate * ac100_clkout_prediv[pre_div].div, > > + prate, NULL, AC100_CLKOUT_DIV_WIDTH, > > + CLK_DIVIDER_POWER_OF_TWO); -> > + if (div >=3D 0) +> > + if (div >= 0) > > + break; -> > + } while (prate !=3D AC100_RTC_32K_RATE && +> > + } while (prate != AC100_RTC_32K_RATE && > > + ac100_clkout_prediv[++pre_div].div); > > + > > + if (div < 0) > > + return div; > > + -> > + pre_div =3D ac100_clkout_prediv[pre_div].val; +> > + pre_div = ac100_clkout_prediv[pre_div].val; > > + > > + regmap_update_bits(clk->regmap, clk->offset, > > + ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT | -> > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_= -SHIFT, +> > + ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT, > > + (div - 1) << AC100_CLKOUT_DIV_SHIFT | > > + (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT); > > + @@ -223,7 +217,7 @@ SHIFT, > > + > > +static int ac100_clkout_prepare(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + return regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, > > + AC100_CLKOUT_EN); @@ -231,14 +225,14 @@ SHIFT, > > + > > +static void ac100_clkout_unprepare(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0); > > +} > > + > > +static int ac100_clkout_is_prepared(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg; > > + > > + regmap_read(clk->regmap, clk->offset, ®); @@ -248,7 +242,7 @@ SHIFT, > > + > > +static u8 ac100_clkout_get_parent(struct clk_hw *hw) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + unsigned int reg; > > + > > + regmap_read(clk->regmap, clk->offset, ®); @@ -258,81 +252,80 @@ SHIFT, > > + > > +static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index) > > +{ -> > + struct ac100_clkout *clk =3D to_ac100_clkout(hw); +> > + struct ac100_clkout *clk = to_ac100_clkout(hw); > > + > > + return regmap_update_bits(clk->regmap, clk->offset, > > + BIT(AC100_CLKOUT_MUX_SHIFT), > > + index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0); > > +} > > + -> > +static const struct clk_ops ac100_clkout_ops =3D { -> > + .prepare =3D ac100_clkout_prepare, -> > + .unprepare =3D ac100_clkout_unprepare, -> > + .is_prepared =3D ac100_clkout_is_prepared, -> > + .recalc_rate =3D ac100_clkout_recalc_rate, -> > + .determine_rate =3D ac100_clkout_determine_rate, -> > + .get_parent =3D ac100_clkout_get_parent, -> > + .set_parent =3D ac100_clkout_set_parent, -> > + .set_rate =3D ac100_clkout_set_rate, +> > +static const struct clk_ops ac100_clkout_ops = { +> > + .prepare = ac100_clkout_prepare, +> > + .unprepare = ac100_clkout_unprepare, +> > + .is_prepared = ac100_clkout_is_prepared, +> > + .recalc_rate = ac100_clkout_recalc_rate, +> > + .determine_rate = ac100_clkout_determine_rate, +> > + .get_parent = ac100_clkout_get_parent, +> > + .set_parent = ac100_clkout_set_parent, +> > + .set_rate = ac100_clkout_set_rate, > > +}; > > + > > +static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip) > > +{ -> > + struct device_node *np =3D chip->dev->of_node; -> > + const char *parents[2] =3D {AC100_RTC_32K_NAME}; +> > + struct device_node *np = chip->dev->of_node; +> > + const char *parents[2] = {AC100_RTC_32K_NAME}; > > + int i, ret; > > + -> > + chip->clk_data =3D devm_kzalloc(chip->dev, sizeof(*chip->clk_data) + +> > + chip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) + > > + sizeof(*chip->clk_data->hws) * > > + AC100_CLKOUT_NUM, > > + GFP_KERNEL); > > + if (!chip->clk_data) > > + return -ENOMEM; > > + -> > + chip->rtc_32k_clk =3D clk_hw_register_fixed_rate(chip->dev, +> > + chip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev, > > + AC100_RTC_32K_NAME, > > + NULL, 0, > > + AC100_RTC_32K_RATE); > > + if (IS_ERR(chip->rtc_32k_clk)) { -> > + ret =3D PTR_ERR(chip->rtc_32k_clk); +> > + ret = PTR_ERR(chip->rtc_32k_clk); > > + dev_err(chip->dev, "Failed to register RTC-32k clock: %d\n", > > + ret); > > + return ret; > > + } > > + -> > + parents[1] =3D of_clk_get_parent_name(np, 0); +> > + parents[1] = of_clk_get_parent_name(np, 0); > > + if (!parents[1]) { > > + dev_err(chip->dev, "Failed to get ADDA 4M clock\n"); > > + return -EINVAL; > > + } > > + -> > + for (i =3D 0; i < AC100_CLKOUT_NUM; i++) { -> > + struct ac100_clkout *clk =3D &chip->clks[i]; -> > + struct clk_init_data init =3D { -> > + .name =3D ac100_clkout_names[i], -> > + .ops =3D &ac100_clkout_ops, -> > + .parent_names =3D parents, -> > + .num_parents =3D ARRAY_SIZE(parents), -> > + .flags =3D 0, +> > + for (i = 0; i < AC100_CLKOUT_NUM; i++) { +> > + struct ac100_clkout *clk = &chip->clks[i]; +> > + struct clk_init_data init = { +> > + .name = ac100_clkout_names[i], +> > + .ops = &ac100_clkout_ops, +> > + .parent_names = parents, +> > + .num_parents = ARRAY_SIZE(parents), +> > + .flags = 0, > > + }; > > + -> > + clk->regmap =3D chip->regmap; -> > + clk->offset =3D AC100_CLKOUT_CTRL1 + i; -> > + clk->hw.init =3D &init; +> > + clk->regmap = chip->regmap; +> > + clk->offset = AC100_CLKOUT_CTRL1 + i; +> > + clk->hw.init = &init; > > + -> > + ret =3D devm_clk_hw_register(chip->dev, &clk->hw); +> > + ret = devm_clk_hw_register(chip->dev, &clk->hw); > > + if (ret) { > > + dev_err(chip->dev, "Failed to register clk '%s': %d\n", > > + init.name, ret); > > + goto err_unregister_rtc_32k; > > + } > > + -> > + chip->clk_data->hws[i] =3D &clk->hw; +> > + chip->clk_data->hws[i] = &clk->hw; > > + } > > + -> > + chip->clk_data->num =3D i; -> > + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_d= -ata); +> > + chip->clk_data->num = i; +> > + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data); > > + if (ret) > > + goto err_unregister_rtc_32k; > > + @@ -353,60 +346,46 @@ ata); > > +/** > > + * RTC related bits > > + */ -> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc= -_tm) +> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm) > > { -> > struct ac100_rtc_dev *chip =3D dev_get_drvdata(dev); -> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device= - *pdev) +> > struct ac100_rtc_dev *chip = dev_get_drvdata(dev); +> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device *pdev) > > return PTR_ERR(chip->rtc); > > } -> > =20 -> > + ret =3D ac100_rtc_register_clks(chip); +> > +> > + ret = ac100_rtc_register_clks(chip); > > + if (ret) > > + return ret; > > + > > dev_info(&pdev->dev, "RTC enabled\n"); -> > =20 +> > > > return 0; > > } -> > =20 +> > > > +static int ac100_rtc_remove(struct platform_device *pdev) > > +{ -> > + struct ac100_rtc_dev *chip =3D platform_get_drvdata(pdev); +> > + struct ac100_rtc_dev *chip = platform_get_drvdata(pdev); > > + > > + ac100_rtc_unregister_clks(chip); > > + > > + return 0; > > +} > > + -> > static const struct of_device_id ac100_rtc_match[] =3D { -> > { .compatible =3D "x-powers,ac100-rtc" }, +> > static const struct of_device_id ac100_rtc_match[] = { +> > { .compatible = "x-powers,ac100-rtc" }, > > { }, > > @@ -313,6 +614,7 @@ MODULE_DEVICE_TABLE(of, ac100_rtc_match); -> > =20 -> > static struct platform_driver ac100_rtc_driver =3D { -> > .probe =3D ac100_rtc_probe, -> > + .remove =3D ac100_rtc_remove, -> > .driver =3D { -> > .name =3D "ac100-rtc", -> > .of_match_table =3D of_match_ptr(ac100_rtc_match), ->=20 +> > +> > static struct platform_driver ac100_rtc_driver = { +> > .probe = ac100_rtc_probe, +> > + .remove = ac100_rtc_remove, +> > .driver = { +> > .name = "ac100-rtc", +> > .of_match_table = of_match_ptr(ac100_rtc_match), +> ---=20 +-- Lee Jones Linaro STMicroelectronics Landing Team Lead -Linaro.org =E2=94=82 Open source software for ARM SoCs +Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog - ---=20 -You received this message because you are subscribed to "rtc-linux". -Membership options at http://groups.google.com/group/rtc-linux . -Please read http://groups.google.com/group/rtc-linux/web/checklist -before submitting a driver. ----=20 -You received this message because you are subscribed to the Google Groups "= -rtc-linux" group. -To unsubscribe from this group and stop receiving emails from it, send an e= -mail to rtc-linux+unsubscribe@googlegroups.com. -For more options, visit https://groups.google.com/d/optout. diff --git a/a/content_digest b/N3/content_digest index a5539bb..6bba50f 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -2,7 +2,7 @@ "ref\01467988422-17934-5-git-send-email-wens@csie.org\0" "ref\020160708162932.GN22202@piout.net\0" "From\0Lee Jones <lee.jones@linaro.org>\0" - "Subject\0[rtc-linux] Re: [PATCH v5 4/7] rtc: ac100: Add clk output support\0" + "Subject\0Re: [PATCH v5 4/7] rtc: ac100: Add clk output support\0" "Date\0Mon, 8 Aug 2016 12:56:51 +0100\0" "To\0Alexandre Belloni <alexandre.belloni@free-electrons.com>\0" "Cc\0Chen-Yu Tsai <wens@csie.org>" @@ -20,27 +20,26 @@ "> > The AC100's RTC side has 3 clock outputs on external pins, which can\n" "> > provide a clock signal to the SoC or other modules, such as WiFi or\n" "> > GSM modules.\n" - "> >=20\n" + "> > \n" "> > Support this with a custom clk driver integrated with the rtc driver.\n" - "> >=20\n" + "> > \n" "> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>\n" "> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>\n" - ">=20\n" + "> \n" "> > ---\n" "> > Changes since v4: none\n" - "> >=20\n" + "> > \n" "> > Changes since v3:\n" - "> >=20\n" + "> > \n" "> > - Renamed clk32k prefixes to clkout, except for the internal 32k clk\n" "> > - Changed default clk output names to \"ac100-cko{1,2,3}-rtc\"\n" "> > - Moved 4M ADDA clk to codec side\n" - "> >=20\n" + "> > \n" "> > Changes since v2: none\n" "> > Changes since v1: none\n" - "> >=20\n" + "> > \n" "> > ---\n" - "> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++=\n" - "++++++++\n" + "> > drivers/rtc/rtc-ac100.c | 302 ++++++++++++++++++++++++++++++++++++++++++++++++\n" "> > 1 file changed, 302 insertions(+)\n" "\n" "Applied, thanks.\n" @@ -51,7 +50,7 @@ "> > +++ b/drivers/rtc/rtc-ac100.c\n" "> > @@ -16,6 +16,7 @@\n" "> > */\n" - "> > =20\n" + "> > \n" "> > #include <linux/bcd.h>\n" "> > +#include <linux/clk-provider.h>\n" "> > #include <linux/device.h>\n" @@ -60,7 +59,7 @@ "> > @@ -31,6 +32,15 @@\n" "> > /* Control register */\n" "> > #define AC100_RTC_CTRL_24HOUR\tBIT(0)\n" - "> > =20\n" + "> > \n" "> > +/* Clock output register bits */\n" "> > +#define AC100_CLKOUT_PRE_DIV_SHIFT\t5\n" "> > +#define AC100_CLKOUT_PRE_DIV_WIDTH\t3\n" @@ -76,21 +75,20 @@ "> > @@ -67,14 +77,292 @@\n" "> > #define AC100_YEAR_MAX\t\t\t\t2069\n" "> > #define AC100_YEAR_OFF\t\t\t\t(AC100_YEAR_MIN - 1900)\n" - "> > =20\n" + "> > \n" "> > +struct ac100_clkout {\n" "> > +\tstruct clk_hw hw;\n" "> > +\tstruct regmap *regmap;\n" "> > +\tu8 offset;\n" "> > +};\n" "> > +\n" - "> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw=\n" - ")\n" + "> > +#define to_ac100_clkout(_hw) container_of(_hw, struct ac100_clkout, hw)\n" "> > +\n" "> > +#define AC100_RTC_32K_NAME\t\"ac100-rtc-32k\"\n" "> > +#define AC100_RTC_32K_RATE\t32768\n" "> > +#define AC100_CLKOUT_NUM\t3\n" "> > +\n" - "> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] =3D {\n" + "> > +static const char * const ac100_clkout_names[AC100_CLKOUT_NUM] = {\n" "> > +\t\"ac100-cko1-rtc\",\n" "> > +\t\"ac100-cko2-rtc\",\n" "> > +\t\"ac100-cko3-rtc\",\n" @@ -107,69 +105,67 @@ "> > +\tstruct ac100_clkout clks[AC100_CLKOUT_NUM];\n" "> > +\tstruct clk_hw_onecell_data *clk_data;\n" "> > };\n" - "> > =20\n" + "> > \n" "> > +/**\n" "> > + * Clock controls for 3 clock output pins\n" "> > + */\n" "> > +\n" - "> > +static const struct clk_div_table ac100_clkout_prediv[] =3D {\n" - "> > +\t{ .val =3D 0, .div =3D 1 },\n" - "> > +\t{ .val =3D 1, .div =3D 2 },\n" - "> > +\t{ .val =3D 2, .div =3D 4 },\n" - "> > +\t{ .val =3D 3, .div =3D 8 },\n" - "> > +\t{ .val =3D 4, .div =3D 16 },\n" - "> > +\t{ .val =3D 5, .div =3D 32 },\n" - "> > +\t{ .val =3D 6, .div =3D 64 },\n" - "> > +\t{ .val =3D 7, .div =3D 122 },\n" + "> > +static const struct clk_div_table ac100_clkout_prediv[] = {\n" + "> > +\t{ .val = 0, .div = 1 },\n" + "> > +\t{ .val = 1, .div = 2 },\n" + "> > +\t{ .val = 2, .div = 4 },\n" + "> > +\t{ .val = 3, .div = 8 },\n" + "> > +\t{ .val = 4, .div = 16 },\n" + "> > +\t{ .val = 5, .div = 32 },\n" + "> > +\t{ .val = 6, .div = 64 },\n" + "> > +\t{ .val = 7, .div = 122 },\n" "> > +\t{ },\n" "> > +};\n" "> > +\n" - "> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz =\n" - "*/\n" + "> > +/* Abuse the fact that one parent is 32768 Hz, and the other is 4 MHz */\n" "> > +static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,\n" "> > +\t\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg, div;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" "> > +\n" "> > +\t/* Handle pre-divider first */\n" - "> > +\tif (prate !=3D AC100_RTC_32K_RATE) {\n" - "> > +\t\tdiv =3D (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &\n" + "> > +\tif (prate != AC100_RTC_32K_RATE) {\n" + "> > +\t\tdiv = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &\n" "> > +\t\t\t((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);\n" - "> > +\t\tprate =3D divider_recalc_rate(hw, prate, div,\n" + "> > +\t\tprate = divider_recalc_rate(hw, prate, div,\n" "> > +\t\t\t\t\t ac100_clkout_prediv, 0);\n" "> > +\t}\n" "> > +\n" - "> > +\tdiv =3D (reg >> AC100_CLKOUT_DIV_SHIFT) &\n" + "> > +\tdiv = (reg >> AC100_CLKOUT_DIV_SHIFT) &\n" "> > +\t\t(BIT(AC100_CLKOUT_DIV_WIDTH) - 1);\n" "> > +\treturn divider_recalc_rate(hw, prate, div, NULL,\n" "> > +\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +}\n" "> > +\n" - "> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long r=\n" - "ate,\n" + "> > +static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,\n" "> > +\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tunsigned long best_rate =3D 0, tmp_rate, tmp_prate;\n" + "> > +\tunsigned long best_rate = 0, tmp_rate, tmp_prate;\n" "> > +\tint i;\n" "> > +\n" - "> > +\tif (prate =3D=3D AC100_RTC_32K_RATE)\n" + "> > +\tif (prate == AC100_RTC_32K_RATE)\n" "> > +\t\treturn divider_round_rate(hw, rate, &prate, NULL,\n" "> > +\t\t\t\t\t AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +\n" - "> > +\tfor (i =3D 0; ac100_clkout_prediv[i].div; i++) {\n" - "> > +\t\ttmp_prate =3D DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);\n" - "> > +\t\ttmp_rate =3D divider_round_rate(hw, rate, &tmp_prate, NULL,\n" + "> > +\tfor (i = 0; ac100_clkout_prediv[i].div; i++) {\n" + "> > +\t\ttmp_prate = DIV_ROUND_UP(prate, ac100_clkout_prediv[i].val);\n" + "> > +\t\ttmp_rate = divider_round_rate(hw, rate, &tmp_prate, NULL,\n" "> > +\t\t\t\t\t AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" "> > +\n" "> > +\t\tif (tmp_rate > rate)\n" "> > +\t\t\tcontinue;\n" "> > +\t\tif (rate - tmp_rate < best_rate - tmp_rate)\n" - "> > +\t\t\tbest_rate =3D tmp_rate;\n" + "> > +\t\t\tbest_rate = tmp_rate;\n" "> > +\t}\n" "> > +\n" "> > +\treturn best_rate;\n" @@ -179,58 +175,56 @@ "> > +\t\t\t\t struct clk_rate_request *req)\n" "> > +{\n" "> > +\tstruct clk_hw *best_parent;\n" - "> > +\tunsigned long best =3D 0;\n" - "> > +\tint i, num_parents =3D clk_hw_get_num_parents(hw);\n" + "> > +\tunsigned long best = 0;\n" + "> > +\tint i, num_parents = clk_hw_get_num_parents(hw);\n" "> > +\n" - "> > +\tfor (i =3D 0; i < num_parents; i++) {\n" - "> > +\t\tstruct clk_hw *parent =3D clk_hw_get_parent_by_index(hw, i);\n" - "> > +\t\tunsigned long tmp, prate =3D clk_hw_get_rate(parent);\n" + "> > +\tfor (i = 0; i < num_parents; i++) {\n" + "> > +\t\tstruct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);\n" + "> > +\t\tunsigned long tmp, prate = clk_hw_get_rate(parent);\n" "> > +\n" - "> > +\t\ttmp =3D ac100_clkout_round_rate(hw, req->rate, prate);\n" + "> > +\t\ttmp = ac100_clkout_round_rate(hw, req->rate, prate);\n" "> > +\n" "> > +\t\tif (tmp > req->rate)\n" "> > +\t\t\tcontinue;\n" "> > +\t\tif (req->rate - tmp < req->rate - best) {\n" - "> > +\t\t\tbest =3D tmp;\n" - "> > +\t\t\tbest_parent =3D parent;\n" + "> > +\t\t\tbest = tmp;\n" + "> > +\t\t\tbest_parent = parent;\n" "> > +\t\t}\n" "> > +\t}\n" "> > +\n" "> > +\tif (!best)\n" "> > +\t\treturn -EINVAL;\n" "> > +\n" - "> > +\treq->best_parent_hw =3D best_parent;\n" - "> > +\treq->best_parent_rate =3D best;\n" - "> > +\treq->rate =3D best;\n" + "> > +\treq->best_parent_hw = best_parent;\n" + "> > +\treq->best_parent_rate = best;\n" + "> > +\treq->rate = best;\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" - "> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate=\n" - ",\n" + "> > +static int ac100_clkout_set_rate(struct clk_hw *hw, unsigned long rate,\n" "> > +\t\t\t\t unsigned long prate)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" - "> > +\tint div =3D 0, pre_div =3D 0;\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" + "> > +\tint div = 0, pre_div = 0;\n" "> > +\n" "> > +\tdo {\n" - "> > +\t\tdiv =3D divider_get_val(rate * ac100_clkout_prediv[pre_div].div,\n" + "> > +\t\tdiv = divider_get_val(rate * ac100_clkout_prediv[pre_div].div,\n" "> > +\t\t\t\t prate, NULL, AC100_CLKOUT_DIV_WIDTH,\n" "> > +\t\t\t\t CLK_DIVIDER_POWER_OF_TWO);\n" - "> > +\t\tif (div >=3D 0)\n" + "> > +\t\tif (div >= 0)\n" "> > +\t\t\tbreak;\n" - "> > +\t} while (prate !=3D AC100_RTC_32K_RATE &&\n" + "> > +\t} while (prate != AC100_RTC_32K_RATE &&\n" "> > +\t\t ac100_clkout_prediv[++pre_div].div);\n" "> > +\n" "> > +\tif (div < 0)\n" "> > +\t\treturn div;\n" "> > +\n" - "> > +\tpre_div =3D ac100_clkout_prediv[pre_div].val;\n" + "> > +\tpre_div = ac100_clkout_prediv[pre_div].val;\n" "> > +\n" "> > +\tregmap_update_bits(clk->regmap, clk->offset,\n" "> > +\t\t\t ((1 << AC100_CLKOUT_DIV_WIDTH) - 1) << AC100_CLKOUT_DIV_SHIFT |\n" - "> > +\t\t\t ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_=\n" - "SHIFT,\n" + "> > +\t\t\t ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1) << AC100_CLKOUT_PRE_DIV_SHIFT,\n" "> > +\t\t\t (div - 1) << AC100_CLKOUT_DIV_SHIFT |\n" "> > +\t\t\t (pre_div - 1) << AC100_CLKOUT_PRE_DIV_SHIFT);\n" "> > +\n" @@ -239,7 +233,7 @@ "> > +\n" "> > +static int ac100_clkout_prepare(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\treturn regmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN,\n" "> > +\t\t\t\t AC100_CLKOUT_EN);\n" @@ -247,14 +241,14 @@ "> > +\n" "> > +static void ac100_clkout_unprepare(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\tregmap_update_bits(clk->regmap, clk->offset, AC100_CLKOUT_EN, 0);\n" "> > +}\n" "> > +\n" "> > +static int ac100_clkout_is_prepared(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" @@ -264,7 +258,7 @@ "> > +\n" "> > +static u8 ac100_clkout_get_parent(struct clk_hw *hw)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\tunsigned int reg;\n" "> > +\n" "> > +\tregmap_read(clk->regmap, clk->offset, ®);\n" @@ -274,81 +268,80 @@ "> > +\n" "> > +static int ac100_clkout_set_parent(struct clk_hw *hw, u8 index)\n" "> > +{\n" - "> > +\tstruct ac100_clkout *clk =3D to_ac100_clkout(hw);\n" + "> > +\tstruct ac100_clkout *clk = to_ac100_clkout(hw);\n" "> > +\n" "> > +\treturn regmap_update_bits(clk->regmap, clk->offset,\n" "> > +\t\t\t\t BIT(AC100_CLKOUT_MUX_SHIFT),\n" "> > +\t\t\t\t index ? BIT(AC100_CLKOUT_MUX_SHIFT) : 0);\n" "> > +}\n" "> > +\n" - "> > +static const struct clk_ops ac100_clkout_ops =3D {\n" - "> > +\t.prepare\t=3D ac100_clkout_prepare,\n" - "> > +\t.unprepare\t=3D ac100_clkout_unprepare,\n" - "> > +\t.is_prepared\t=3D ac100_clkout_is_prepared,\n" - "> > +\t.recalc_rate\t=3D ac100_clkout_recalc_rate,\n" - "> > +\t.determine_rate\t=3D ac100_clkout_determine_rate,\n" - "> > +\t.get_parent\t=3D ac100_clkout_get_parent,\n" - "> > +\t.set_parent\t=3D ac100_clkout_set_parent,\n" - "> > +\t.set_rate\t=3D ac100_clkout_set_rate,\n" + "> > +static const struct clk_ops ac100_clkout_ops = {\n" + "> > +\t.prepare\t= ac100_clkout_prepare,\n" + "> > +\t.unprepare\t= ac100_clkout_unprepare,\n" + "> > +\t.is_prepared\t= ac100_clkout_is_prepared,\n" + "> > +\t.recalc_rate\t= ac100_clkout_recalc_rate,\n" + "> > +\t.determine_rate\t= ac100_clkout_determine_rate,\n" + "> > +\t.get_parent\t= ac100_clkout_get_parent,\n" + "> > +\t.set_parent\t= ac100_clkout_set_parent,\n" + "> > +\t.set_rate\t= ac100_clkout_set_rate,\n" "> > +};\n" "> > +\n" "> > +static int ac100_rtc_register_clks(struct ac100_rtc_dev *chip)\n" "> > +{\n" - "> > +\tstruct device_node *np =3D chip->dev->of_node;\n" - "> > +\tconst char *parents[2] =3D {AC100_RTC_32K_NAME};\n" + "> > +\tstruct device_node *np = chip->dev->of_node;\n" + "> > +\tconst char *parents[2] = {AC100_RTC_32K_NAME};\n" "> > +\tint i, ret;\n" "> > +\n" - "> > +\tchip->clk_data =3D devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +\n" + "> > +\tchip->clk_data = devm_kzalloc(chip->dev, sizeof(*chip->clk_data) +\n" "> > +\t\t\t\t\t\t sizeof(*chip->clk_data->hws) *\n" "> > +\t\t\t\t\t\t AC100_CLKOUT_NUM,\n" "> > +\t\t\t\t\t\t GFP_KERNEL);\n" "> > +\tif (!chip->clk_data)\n" "> > +\t\treturn -ENOMEM;\n" "> > +\n" - "> > +\tchip->rtc_32k_clk =3D clk_hw_register_fixed_rate(chip->dev,\n" + "> > +\tchip->rtc_32k_clk = clk_hw_register_fixed_rate(chip->dev,\n" "> > +\t\t\t\t\t\t AC100_RTC_32K_NAME,\n" "> > +\t\t\t\t\t\t NULL, 0,\n" "> > +\t\t\t\t\t\t AC100_RTC_32K_RATE);\n" "> > +\tif (IS_ERR(chip->rtc_32k_clk)) {\n" - "> > +\t\tret =3D PTR_ERR(chip->rtc_32k_clk);\n" + "> > +\t\tret = PTR_ERR(chip->rtc_32k_clk);\n" "> > +\t\tdev_err(chip->dev, \"Failed to register RTC-32k clock: %d\\n\",\n" "> > +\t\t\tret);\n" "> > +\t\treturn ret;\n" "> > +\t}\n" "> > +\n" - "> > +\tparents[1] =3D of_clk_get_parent_name(np, 0);\n" + "> > +\tparents[1] = of_clk_get_parent_name(np, 0);\n" "> > +\tif (!parents[1]) {\n" "> > +\t\tdev_err(chip->dev, \"Failed to get ADDA 4M clock\\n\");\n" "> > +\t\treturn -EINVAL;\n" "> > +\t}\n" "> > +\n" - "> > +\tfor (i =3D 0; i < AC100_CLKOUT_NUM; i++) {\n" - "> > +\t\tstruct ac100_clkout *clk =3D &chip->clks[i];\n" - "> > +\t\tstruct clk_init_data init =3D {\n" - "> > +\t\t\t.name =3D ac100_clkout_names[i],\n" - "> > +\t\t\t.ops =3D &ac100_clkout_ops,\n" - "> > +\t\t\t.parent_names =3D parents,\n" - "> > +\t\t\t.num_parents =3D ARRAY_SIZE(parents),\n" - "> > +\t\t\t.flags =3D 0,\n" + "> > +\tfor (i = 0; i < AC100_CLKOUT_NUM; i++) {\n" + "> > +\t\tstruct ac100_clkout *clk = &chip->clks[i];\n" + "> > +\t\tstruct clk_init_data init = {\n" + "> > +\t\t\t.name = ac100_clkout_names[i],\n" + "> > +\t\t\t.ops = &ac100_clkout_ops,\n" + "> > +\t\t\t.parent_names = parents,\n" + "> > +\t\t\t.num_parents = ARRAY_SIZE(parents),\n" + "> > +\t\t\t.flags = 0,\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tclk->regmap =3D chip->regmap;\n" - "> > +\t\tclk->offset =3D AC100_CLKOUT_CTRL1 + i;\n" - "> > +\t\tclk->hw.init =3D &init;\n" + "> > +\t\tclk->regmap = chip->regmap;\n" + "> > +\t\tclk->offset = AC100_CLKOUT_CTRL1 + i;\n" + "> > +\t\tclk->hw.init = &init;\n" "> > +\n" - "> > +\t\tret =3D devm_clk_hw_register(chip->dev, &clk->hw);\n" + "> > +\t\tret = devm_clk_hw_register(chip->dev, &clk->hw);\n" "> > +\t\tif (ret) {\n" "> > +\t\t\tdev_err(chip->dev, \"Failed to register clk '%s': %d\\n\",\n" "> > +\t\t\t\tinit.name, ret);\n" "> > +\t\t\tgoto err_unregister_rtc_32k;\n" "> > +\t\t}\n" "> > +\n" - "> > +\t\tchip->clk_data->hws[i] =3D &clk->hw;\n" + "> > +\t\tchip->clk_data->hws[i] = &clk->hw;\n" "> > +\t}\n" "> > +\n" - "> > +\tchip->clk_data->num =3D i;\n" - "> > +\tret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_d=\n" - "ata);\n" + "> > +\tchip->clk_data->num = i;\n" + "> > +\tret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, chip->clk_data);\n" "> > +\tif (ret)\n" "> > +\t\tgoto err_unregister_rtc_32k;\n" "> > +\n" @@ -369,62 +362,48 @@ "> > +/**\n" "> > + * RTC related bits\n" "> > + */\n" - "> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc=\n" - "_tm)\n" + "> > static int ac100_rtc_get_time(struct device *dev, struct rtc_time *rtc_tm)\n" "> > {\n" - "> > \tstruct ac100_rtc_dev *chip =3D dev_get_drvdata(dev);\n" - "> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device=\n" - " *pdev)\n" + "> > \tstruct ac100_rtc_dev *chip = dev_get_drvdata(dev);\n" + "> > @@ -300,11 +588,24 @@ static int ac100_rtc_probe(struct platform_device *pdev)\n" "> > \t\treturn PTR_ERR(chip->rtc);\n" "> > \t}\n" - "> > =20\n" - "> > +\tret =3D ac100_rtc_register_clks(chip);\n" + "> > \n" + "> > +\tret = ac100_rtc_register_clks(chip);\n" "> > +\tif (ret)\n" "> > +\t\treturn ret;\n" "> > +\n" "> > \tdev_info(&pdev->dev, \"RTC enabled\\n\");\n" - "> > =20\n" + "> > \n" "> > \treturn 0;\n" "> > }\n" - "> > =20\n" + "> > \n" "> > +static int ac100_rtc_remove(struct platform_device *pdev)\n" "> > +{\n" - "> > +\tstruct ac100_rtc_dev *chip =3D platform_get_drvdata(pdev);\n" + "> > +\tstruct ac100_rtc_dev *chip = platform_get_drvdata(pdev);\n" "> > +\n" "> > +\tac100_rtc_unregister_clks(chip);\n" "> > +\n" "> > +\treturn 0;\n" "> > +}\n" "> > +\n" - "> > static const struct of_device_id ac100_rtc_match[] =3D {\n" - "> > \t{ .compatible =3D \"x-powers,ac100-rtc\" },\n" + "> > static const struct of_device_id ac100_rtc_match[] = {\n" + "> > \t{ .compatible = \"x-powers,ac100-rtc\" },\n" "> > \t{ },\n" "> > @@ -313,6 +614,7 @@ MODULE_DEVICE_TABLE(of, ac100_rtc_match);\n" - "> > =20\n" - "> > static struct platform_driver ac100_rtc_driver =3D {\n" - "> > \t.probe\t\t=3D ac100_rtc_probe,\n" - "> > +\t.remove\t\t=3D ac100_rtc_remove,\n" - "> > \t.driver\t\t=3D {\n" - "> > \t\t.name\t\t=3D \"ac100-rtc\",\n" - "> > \t\t.of_match_table\t=3D of_match_ptr(ac100_rtc_match),\n" - ">=20\n" + "> > \n" + "> > static struct platform_driver ac100_rtc_driver = {\n" + "> > \t.probe\t\t= ac100_rtc_probe,\n" + "> > +\t.remove\t\t= ac100_rtc_remove,\n" + "> > \t.driver\t\t= {\n" + "> > \t\t.name\t\t= \"ac100-rtc\",\n" + "> > \t\t.of_match_table\t= of_match_ptr(ac100_rtc_match),\n" + "> \n" "\n" - "--=20\n" + "-- \n" "Lee Jones\n" "Linaro STMicroelectronics Landing Team Lead\n" - "Linaro.org =E2=94=82 Open source software for ARM SoCs\n" - "Follow Linaro: Facebook | Twitter | Blog\n" - "\n" - "--=20\n" - "You received this message because you are subscribed to \"rtc-linux\".\n" - "Membership options at http://groups.google.com/group/rtc-linux .\n" - "Please read http://groups.google.com/group/rtc-linux/web/checklist\n" - "before submitting a driver.\n" - "---=20\n" - "You received this message because you are subscribed to the Google Groups \"=\n" - "rtc-linux\" group.\n" - "To unsubscribe from this group and stop receiving emails from it, send an e=\n" - "mail to rtc-linux+unsubscribe@googlegroups.com.\n" - For more options, visit https://groups.google.com/d/optout. + "Linaro.org \342\224\202 Open source software for ARM SoCs\n" + Follow Linaro: Facebook | Twitter | Blog -ef9ae234c7069853050b709159a4cc410ba093e6b4d3e4c9fa41c93aace225c1 +e18166f67d8b67fbbabbbec9643a923201cbf2a40292bfb4c45345ba62a4c292
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