From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lee Jones Subject: Re: [RESEND v2 01/10] mfd: stmpe: Add STMPE_IDX_SYS_CTRL/2 enum Date: Wed, 10 Aug 2016 09:28:49 +0100 Message-ID: <20160810082849.GG1581@dell> References: <1470814755-19447-1-git-send-email-patrice.chotard@st.com> <1470814755-19447-2-git-send-email-patrice.chotard@st.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1470814755-19447-2-git-send-email-patrice.chotard@st.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: patrice.chotard@st.com Cc: gnurou@gmail.com, amelie.delaunay@st.com, vireshk@kernel.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org, thierry.reding@gmail.com, kernel@pengutronix.de, dinguyen@opensource.altera.com, shawnguo@kernel.org, shiraz.linux.kernel@gmail.com, linux-arm-kernel@lists.infradead.org List-Id: linux-gpio@vger.kernel.org T24gV2VkLCAxMCBBdWcgMjAxNiwgcGF0cmljZS5jaG90YXJkQHN0LmNvbSB3cm90ZToKCj4gRnJv bTogUGF0cmljZSBDaG90YXJkIDxwYXRyaWNlLmNob3RhcmRAc3QuY29tPgo+IAo+IEFzIFNUTVBF MTgwMS8xNjAxLzI0eHggaGFzIGEgU1lTX0NUUkwgcmVnaXN0ZXIgYW5kCj4gU1RNUEUxNjAxLzI0 MDMgaGFzIGV2ZW4gYSBTWVNfQ1RSTDIgcmVnaXN0ZXIsIGFkZAo+IFNUTVBFX0lEWF9TWVNfQ1RS TC8yIGFuZCB1cGRhdGUgZHJpdmVyIGNvZGUgYWNjb3JkaW5nbHkKPiAKPiBUaGlzIHVwZGF0ZSBw cmVwYXJlcyB0aGUgZ3JvdW5kIGZvciBub3QgeWV0IHN1cHBvcnRlZCBTVE1QRTE2MDAKPiB3aGlj aCBzaGFyZSBzaW1pbGFyIFJFR19TWVNfQ1RSTCByZWdpc3Rlci4KPiAKPiBTaWduZWQtb2ZmLWJ5 OiBQYXRyaWNlIENob3RhcmQgPHBhdHJpY2UuY2hvdGFyZEBzdC5jb20+Cj4gQWNrZWQtYnk6IExp bnVzIFdhbGxlaWogPGxpbnVzLndhbGxlaWpAbGluYXJvLm9yZz4KPiBBY2tlZC1ieTogTGVlIEpv bmVzIDxsZWUuam9uZXNAbGluYXJvLm9yZz4KPiAtLS0KPiAgZHJpdmVycy9tZmQvc3RtcGUuYyAg ICAgICB8IDIxICsrKysrKysrKysrKysrLS0tLS0tLQo+ICBkcml2ZXJzL21mZC9zdG1wZS5oICAg ICAgIHwgIDIgKysKPiAgaW5jbHVkZS9saW51eC9tZmQvc3RtcGUuaCB8ICAyICsrCj4gIDMgZmls ZXMgY2hhbmdlZCwgMTggaW5zZXJ0aW9ucygrKSwgNyBkZWxldGlvbnMoLSkKCkFwcGxpZWQsIHRo YW5rcy4KCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbWZkL3N0bXBlLmMgYi9kcml2ZXJzL21mZC9z dG1wZS5jCj4gaW5kZXggZmI4ZjllOC4uYzU1M2I3MyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL21m ZC9zdG1wZS5jCj4gKysrIGIvZHJpdmVycy9tZmQvc3RtcGUuYwo+IEBAIC00NDgsNiArNDQ4LDgg QEAgc3RhdGljIGNvbnN0IHN0cnVjdCBtZmRfY2VsbCBzdG1wZV90c19jZWxsID0gewo+ICAKPiAg c3RhdGljIGNvbnN0IHU4IHN0bXBlODExX3JlZ3NbXSA9IHsKPiAgCVtTVE1QRV9JRFhfQ0hJUF9J RF0JPSBTVE1QRTgxMV9SRUdfQ0hJUF9JRCwKPiArCVtTVE1QRV9JRFhfU1lTX0NUUkxdCT0gU1RN UEU4MTFfUkVHX1NZU19DVFJMLAo+ICsJW1NUTVBFX0lEWF9TWVNfQ1RSTDJdCT0gU1RNUEU4MTFf UkVHX1NZU19DVFJMMiwKPiAgCVtTVE1QRV9JRFhfSUNSX0xTQl0JPSBTVE1QRTgxMV9SRUdfSU5U X0NUUkwsCj4gIAlbU1RNUEVfSURYX0lFUl9MU0JdCT0gU1RNUEU4MTFfUkVHX0lOVF9FTiwKPiAg CVtTVE1QRV9JRFhfSVNSX01TQl0JPSBTVE1QRTgxMV9SRUdfSU5UX1NUQSwKPiBAQCAtNDkwLDcg KzQ5Miw3IEBAIHN0YXRpYyBpbnQgc3RtcGU4MTFfZW5hYmxlKHN0cnVjdCBzdG1wZSAqc3RtcGUs IHVuc2lnbmVkIGludCBibG9ja3MsCj4gIAlpZiAoYmxvY2tzICYgU1RNUEVfQkxPQ0tfVE9VQ0hT Q1JFRU4pCj4gIAkJbWFzayB8PSBTVE1QRTgxMV9TWVNfQ1RSTDJfVFNDX09GRjsKPiAgCj4gLQly ZXR1cm4gX19zdG1wZV9zZXRfYml0cyhzdG1wZSwgU1RNUEU4MTFfUkVHX1NZU19DVFJMMiwgbWFz aywKPiArCXJldHVybiBfX3N0bXBlX3NldF9iaXRzKHN0bXBlLCBzdG1wZS0+cmVnc1tTVE1QRV9J RFhfU1lTX0NUUkwyXSwgbWFzaywKPiAgCQkJCWVuYWJsZSA/IDAgOiBtYXNrKTsKPiAgfQo+ICAK PiBAQCAtNTM1LDYgKzUzNyw4IEBAIHN0YXRpYyBzdHJ1Y3Qgc3RtcGVfdmFyaWFudF9pbmZvIHN0 bXBlNjEwID0gewo+ICAKPiAgc3RhdGljIGNvbnN0IHU4IHN0bXBlMTYwMV9yZWdzW10gPSB7Cj4g IAlbU1RNUEVfSURYX0NISVBfSURdCT0gU1RNUEUxNjAxX1JFR19DSElQX0lELAo+ICsJW1NUTVBF X0lEWF9TWVNfQ1RSTF0JPSBTVE1QRTE2MDFfUkVHX1NZU19DVFJMLAo+ICsJW1NUTVBFX0lEWF9T WVNfQ1RSTDJdCT0gU1RNUEUxNjAxX1JFR19TWVNfQ1RSTDIsCj4gIAlbU1RNUEVfSURYX0lDUl9M U0JdCT0gU1RNUEUxNjAxX1JFR19JQ1JfTFNCLAo+ICAJW1NUTVBFX0lEWF9JRVJfTFNCXQk9IFNU TVBFMTYwMV9SRUdfSUVSX0xTQiwKPiAgCVtTVE1QRV9JRFhfSVNSX01TQl0JPSBTVE1QRTE2MDFf UkVHX0lTUl9NU0IsCj4gQEAgLTYxOSwxMyArNjIzLDEzIEBAIHN0YXRpYyBpbnQgc3RtcGUxNjAx X2F1dG9zbGVlcChzdHJ1Y3Qgc3RtcGUgKnN0bXBlLAo+ICAJCXJldHVybiB0aW1lb3V0Owo+ICAJ fQo+ICAKPiAtCXJldCA9IF9fc3RtcGVfc2V0X2JpdHMoc3RtcGUsIFNUTVBFMTYwMV9SRUdfU1lT X0NUUkwyLAo+ICsJcmV0ID0gX19zdG1wZV9zZXRfYml0cyhzdG1wZSwgc3RtcGUtPnJlZ3NbU1RN UEVfSURYX1NZU19DVFJMMl0sCj4gIAkJCVNUTVBFMTYwMV9BVVRPU0xFRVBfVElNRU9VVF9NQVNL LAo+ICAJCQl0aW1lb3V0KTsKPiAgCWlmIChyZXQgPCAwKQo+ICAJCXJldHVybiByZXQ7Cj4gIAo+ IC0JcmV0dXJuIF9fc3RtcGVfc2V0X2JpdHMoc3RtcGUsIFNUTVBFMTYwMV9SRUdfU1lTX0NUUkwy LAo+ICsJcmV0dXJuIF9fc3RtcGVfc2V0X2JpdHMoc3RtcGUsIHN0bXBlLT5yZWdzW1NUTVBFX0lE WF9TWVNfQ1RSTDJdLAo+ICAJCQlTVFBNRTE2MDFfQVVUT1NMRUVQX0VOQUJMRSwKPiAgCQkJU1RQ TUUxNjAxX0FVVE9TTEVFUF9FTkFCTEUpOwo+ICB9Cj4gQEAgLTY1MCw3ICs2NTQsNyBAQCBzdGF0 aWMgaW50IHN0bXBlMTYwMV9lbmFibGUoc3RydWN0IHN0bXBlICpzdG1wZSwgdW5zaWduZWQgaW50 IGJsb2NrcywKPiAgCWVsc2UKPiAgCQltYXNrICY9IH5TVE1QRTE2MDFfU1lTX0NUUkxfRU5BQkxF X1NQV007Cj4gIAo+IC0JcmV0dXJuIF9fc3RtcGVfc2V0X2JpdHMoc3RtcGUsIFNUTVBFMTYwMV9S RUdfU1lTX0NUUkwsIG1hc2ssCj4gKwlyZXR1cm4gX19zdG1wZV9zZXRfYml0cyhzdG1wZSwgc3Rt cGUtPnJlZ3NbU1RNUEVfSURYX1NZU19DVFJMXSwgbWFzaywKPiAgCQkJCWVuYWJsZSA/IG1hc2sg OiAwKTsKPiAgfQo+ICAKPiBAQCAtNjg5LDYgKzY5Myw3IEBAIHN0YXRpYyBzdHJ1Y3Qgc3RtcGVf dmFyaWFudF9pbmZvIHN0bXBlMTYwMSA9IHsKPiAgICovCj4gIHN0YXRpYyBjb25zdCB1OCBzdG1w ZTE4MDFfcmVnc1tdID0gewo+ICAJW1NUTVBFX0lEWF9DSElQX0lEXQk9IFNUTVBFMTgwMV9SRUdf Q0hJUF9JRCwKPiArCVtTVE1QRV9JRFhfU1lTX0NUUkxdCT0gU1RNUEUxODAxX1JFR19TWVNfQ1RS TCwKPiAgCVtTVE1QRV9JRFhfSUNSX0xTQl0JPSBTVE1QRTE4MDFfUkVHX0lOVF9DVFJMX0xPVywK PiAgCVtTVE1QRV9JRFhfSUVSX0xTQl0JPSBTVE1QRTE4MDFfUkVHX0lOVF9FTl9NQVNLX0xPVywK PiAgCVtTVE1QRV9JRFhfSVNSX0xTQl0JPSBTVE1QRTE4MDFfUkVHX0lOVF9TVEFfTE9XLAo+IEBA IC03MzUsMTQgKzc0MCwxNCBAQCBzdGF0aWMgaW50IHN0bXBlMTgwMV9yZXNldChzdHJ1Y3Qgc3Rt cGUgKnN0bXBlKQo+ICAJdW5zaWduZWQgbG9uZyB0aW1lb3V0Owo+ICAJaW50IHJldCA9IDA7Cj4g IAo+IC0JcmV0ID0gX19zdG1wZV9zZXRfYml0cyhzdG1wZSwgU1RNUEUxODAxX1JFR19TWVNfQ1RS TCwKPiArCXJldCA9IF9fc3RtcGVfc2V0X2JpdHMoc3RtcGUsIHN0bXBlLT5yZWdzW1NUTVBFX0lE WF9TWVNfQ1RSTF0sCj4gIAkJU1RNUEUxODAxX01TS19TWVNfQ1RSTF9SRVNFVCwgU1RNUEUxODAx X01TS19TWVNfQ1RSTF9SRVNFVCk7Cj4gIAlpZiAocmV0IDwgMCkKPiAgCQlyZXR1cm4gcmV0Owo+ ICAKPiAgCXRpbWVvdXQgPSBqaWZmaWVzICsgbXNlY3NfdG9famlmZmllcygxMDApOwo+ICAJd2hp bGUgKHRpbWVfYmVmb3JlKGppZmZpZXMsIHRpbWVvdXQpKSB7Cj4gLQkJcmV0ID0gX19zdG1wZV9y ZWdfcmVhZChzdG1wZSwgU1RNUEUxODAxX1JFR19TWVNfQ1RSTCk7Cj4gKwkJcmV0ID0gX19zdG1w ZV9yZWdfcmVhZChzdG1wZSwgc3RtcGUtPnJlZ3NbU1RNUEVfSURYX1NZU19DVFJMXSk7Cj4gIAkJ aWYgKHJldCA8IDApCj4gIAkJCXJldHVybiByZXQ7Cj4gIAkJaWYgKCEocmV0ICYgU1RNUEUxODAx X01TS19TWVNfQ1RSTF9SRVNFVCkpCj4gQEAgLTc3Myw2ICs3NzgsOCBAQCBzdGF0aWMgc3RydWN0 IHN0bXBlX3ZhcmlhbnRfaW5mbyBzdG1wZTE4MDEgPSB7Cj4gIAo+ICBzdGF0aWMgY29uc3QgdTgg c3RtcGUyNHh4X3JlZ3NbXSA9IHsKPiAgCVtTVE1QRV9JRFhfQ0hJUF9JRF0JPSBTVE1QRTI0WFhf UkVHX0NISVBfSUQsCj4gKwlbU1RNUEVfSURYX1NZU19DVFJMXQk9IFNUTVBFMjRYWF9SRUdfU1lT X0NUUkwsCj4gKwlbU1RNUEVfSURYX1NZU19DVFJMMl0JPSBTVE1QRTI0WFhfUkVHX1NZU19DVFJM MiwKPiAgCVtTVE1QRV9JRFhfSUNSX0xTQl0JPSBTVE1QRTI0WFhfUkVHX0lDUl9MU0IsCj4gIAlb U1RNUEVfSURYX0lFUl9MU0JdCT0gU1RNUEUyNFhYX1JFR19JRVJfTFNCLAo+ICAJW1NUTVBFX0lE WF9JU1JfTVNCXQk9IFNUTVBFMjRYWF9SRUdfSVNSX01TQiwKPiBAQCAtODE5LDcgKzgyNiw3IEBA IHN0YXRpYyBpbnQgc3RtcGUyNHh4X2VuYWJsZShzdHJ1Y3Qgc3RtcGUgKnN0bXBlLCB1bnNpZ25l ZCBpbnQgYmxvY2tzLAo+ICAJaWYgKGJsb2NrcyAmIFNUTVBFX0JMT0NLX0tFWVBBRCkKPiAgCQlt YXNrIHw9IFNUTVBFMjRYWF9TWVNfQ1RSTF9FTkFCTEVfS1BDOwo+ICAKPiAtCXJldHVybiBfX3N0 bXBlX3NldF9iaXRzKHN0bXBlLCBTVE1QRTI0WFhfUkVHX1NZU19DVFJMLCBtYXNrLAo+ICsJcmV0 dXJuIF9fc3RtcGVfc2V0X2JpdHMoc3RtcGUsIHN0bXBlLT5yZWdzW1NUTVBFX0lEWF9TWVNfQ1RS TF0sIG1hc2ssCj4gIAkJCQllbmFibGUgPyBtYXNrIDogMCk7Cj4gIH0KPiAgCj4gZGlmZiAtLWdp dCBhL2RyaXZlcnMvbWZkL3N0bXBlLmggYi9kcml2ZXJzL21mZC9zdG1wZS5oCj4gaW5kZXggODRh ZGI0Ni4uNDA2ZjlmMiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL21mZC9zdG1wZS5oCj4gKysrIGIv ZHJpdmVycy9tZmQvc3RtcGUuaAo+IEBAIC0xMzgsNiArMTM4LDcgQEAgaW50IHN0bXBlX3JlbW92 ZShzdHJ1Y3Qgc3RtcGUgKnN0bXBlKTsKPiAgI2RlZmluZSBTVE1QRTgxMV9OUl9JTlRFUk5BTF9J UlFTCTgKPiAgCj4gICNkZWZpbmUgU1RNUEU4MTFfUkVHX0NISVBfSUQJCTB4MDAKPiArI2RlZmlu ZSBTVE1QRTgxMV9SRUdfU1lTX0NUUkwJCTB4MDMKPiAgI2RlZmluZSBTVE1QRTgxMV9SRUdfU1lT X0NUUkwyCQkweDA0Cj4gICNkZWZpbmUgU1RNUEU4MTFfUkVHX1NQSV9DRkcJCTB4MDgKPiAgI2Rl ZmluZSBTVE1QRTgxMV9SRUdfSU5UX0NUUkwJCTB4MDkKPiBAQCAtMjY0LDYgKzI2NSw3IEBAIGlu dCBzdG1wZV9yZW1vdmUoc3RydWN0IHN0bXBlICpzdG1wZSk7Cj4gICNkZWZpbmUgU1RNUEUyNFhY X05SX0lOVEVSTkFMX0lSUVMJOQo+ICAKPiAgI2RlZmluZSBTVE1QRTI0WFhfUkVHX1NZU19DVFJM CQkweDAyCj4gKyNkZWZpbmUgU1RNUEUyNFhYX1JFR19TWVNfQ1RSTDIJCTB4MDMKPiAgI2RlZmlu ZSBTVE1QRTI0WFhfUkVHX0lDUl9MU0IJCTB4MTEKPiAgI2RlZmluZSBTVE1QRTI0WFhfUkVHX0lF Ul9MU0IJCTB4MTMKPiAgI2RlZmluZSBTVE1QRTI0WFhfUkVHX0lTUl9NU0IJCTB4MTQKPiBkaWZm IC0tZ2l0IGEvaW5jbHVkZS9saW51eC9tZmQvc3RtcGUuaCBiL2luY2x1ZGUvbGludXgvbWZkL3N0 bXBlLmgKPiBpbmRleCBjYjgzODgzLi42YzY2OTBmIDEwMDY0NAo+IC0tLSBhL2luY2x1ZGUvbGlu dXgvbWZkL3N0bXBlLmgKPiArKysgYi9pbmNsdWRlL2xpbnV4L21mZC9zdG1wZS5oCj4gQEAgLTM5 LDYgKzM5LDggQEAgZW51bSBzdG1wZV9wYXJ0bnVtIHsKPiAgICovCj4gIGVudW0gewo+ICAJU1RN UEVfSURYX0NISVBfSUQsCj4gKwlTVE1QRV9JRFhfU1lTX0NUUkwsCj4gKwlTVE1QRV9JRFhfU1lT X0NUUkwyLAo+ICAJU1RNUEVfSURYX0lDUl9MU0IsCj4gIAlTVE1QRV9JRFhfSUVSX0xTQiwKPiAg CVNUTVBFX0lEWF9JU1JfTFNCLAoKLS0gCkxlZSBKb25lcwpMaW5hcm8gU1RNaWNyb2VsZWN0cm9u aWNzIExhbmRpbmcgVGVhbSBMZWFkCkxpbmFyby5vcmcg4pSCIE9wZW4gc291cmNlIHNvZnR3YXJl IGZvciBBUk0gU29DcwpGb2xsb3cgTGluYXJvOiBGYWNlYm9vayB8IFR3aXR0ZXIgfCBCbG9nCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0t a2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcK aHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2Vy bmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Wed, 10 Aug 2016 09:28:49 +0100 Subject: [RESEND v2 01/10] mfd: stmpe: Add STMPE_IDX_SYS_CTRL/2 enum In-Reply-To: <1470814755-19447-2-git-send-email-patrice.chotard@st.com> References: <1470814755-19447-1-git-send-email-patrice.chotard@st.com> <1470814755-19447-2-git-send-email-patrice.chotard@st.com> Message-ID: <20160810082849.GG1581@dell> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, 10 Aug 2016, patrice.chotard at st.com wrote: > From: Patrice Chotard > > As STMPE1801/1601/24xx has a SYS_CTRL register and > STMPE1601/2403 has even a SYS_CTRL2 register, add > STMPE_IDX_SYS_CTRL/2 and update driver code accordingly > > This update prepares the ground for not yet supported STMPE1600 > which share similar REG_SYS_CTRL register. > > Signed-off-by: Patrice Chotard > Acked-by: Linus Walleij > Acked-by: Lee Jones > --- > drivers/mfd/stmpe.c | 21 ++++++++++++++------- > drivers/mfd/stmpe.h | 2 ++ > include/linux/mfd/stmpe.h | 2 ++ > 3 files changed, 18 insertions(+), 7 deletions(-) Applied, thanks. > diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c > index fb8f9e8..c553b73 100644 > --- a/drivers/mfd/stmpe.c > +++ b/drivers/mfd/stmpe.c > @@ -448,6 +448,8 @@ static const struct mfd_cell stmpe_ts_cell = { > > static const u8 stmpe811_regs[] = { > [STMPE_IDX_CHIP_ID] = STMPE811_REG_CHIP_ID, > + [STMPE_IDX_SYS_CTRL] = STMPE811_REG_SYS_CTRL, > + [STMPE_IDX_SYS_CTRL2] = STMPE811_REG_SYS_CTRL2, > [STMPE_IDX_ICR_LSB] = STMPE811_REG_INT_CTRL, > [STMPE_IDX_IER_LSB] = STMPE811_REG_INT_EN, > [STMPE_IDX_ISR_MSB] = STMPE811_REG_INT_STA, > @@ -490,7 +492,7 @@ static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, > if (blocks & STMPE_BLOCK_TOUCHSCREEN) > mask |= STMPE811_SYS_CTRL2_TSC_OFF; > > - return __stmpe_set_bits(stmpe, STMPE811_REG_SYS_CTRL2, mask, > + return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], mask, > enable ? 0 : mask); > } > > @@ -535,6 +537,8 @@ static struct stmpe_variant_info stmpe610 = { > > static const u8 stmpe1601_regs[] = { > [STMPE_IDX_CHIP_ID] = STMPE1601_REG_CHIP_ID, > + [STMPE_IDX_SYS_CTRL] = STMPE1601_REG_SYS_CTRL, > + [STMPE_IDX_SYS_CTRL2] = STMPE1601_REG_SYS_CTRL2, > [STMPE_IDX_ICR_LSB] = STMPE1601_REG_ICR_LSB, > [STMPE_IDX_IER_LSB] = STMPE1601_REG_IER_LSB, > [STMPE_IDX_ISR_MSB] = STMPE1601_REG_ISR_MSB, > @@ -619,13 +623,13 @@ static int stmpe1601_autosleep(struct stmpe *stmpe, > return timeout; > } > > - ret = __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2, > + ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], > STMPE1601_AUTOSLEEP_TIMEOUT_MASK, > timeout); > if (ret < 0) > return ret; > > - return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL2, > + return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL2], > STPME1601_AUTOSLEEP_ENABLE, > STPME1601_AUTOSLEEP_ENABLE); > } > @@ -650,7 +654,7 @@ static int stmpe1601_enable(struct stmpe *stmpe, unsigned int blocks, > else > mask &= ~STMPE1601_SYS_CTRL_ENABLE_SPWM; > > - return __stmpe_set_bits(stmpe, STMPE1601_REG_SYS_CTRL, mask, > + return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, > enable ? mask : 0); > } > > @@ -689,6 +693,7 @@ static struct stmpe_variant_info stmpe1601 = { > */ > static const u8 stmpe1801_regs[] = { > [STMPE_IDX_CHIP_ID] = STMPE1801_REG_CHIP_ID, > + [STMPE_IDX_SYS_CTRL] = STMPE1801_REG_SYS_CTRL, > [STMPE_IDX_ICR_LSB] = STMPE1801_REG_INT_CTRL_LOW, > [STMPE_IDX_IER_LSB] = STMPE1801_REG_INT_EN_MASK_LOW, > [STMPE_IDX_ISR_LSB] = STMPE1801_REG_INT_STA_LOW, > @@ -735,14 +740,14 @@ static int stmpe1801_reset(struct stmpe *stmpe) > unsigned long timeout; > int ret = 0; > > - ret = __stmpe_set_bits(stmpe, STMPE1801_REG_SYS_CTRL, > + ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], > STMPE1801_MSK_SYS_CTRL_RESET, STMPE1801_MSK_SYS_CTRL_RESET); > if (ret < 0) > return ret; > > timeout = jiffies + msecs_to_jiffies(100); > while (time_before(jiffies, timeout)) { > - ret = __stmpe_reg_read(stmpe, STMPE1801_REG_SYS_CTRL); > + ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]); > if (ret < 0) > return ret; > if (!(ret & STMPE1801_MSK_SYS_CTRL_RESET)) > @@ -773,6 +778,8 @@ static struct stmpe_variant_info stmpe1801 = { > > static const u8 stmpe24xx_regs[] = { > [STMPE_IDX_CHIP_ID] = STMPE24XX_REG_CHIP_ID, > + [STMPE_IDX_SYS_CTRL] = STMPE24XX_REG_SYS_CTRL, > + [STMPE_IDX_SYS_CTRL2] = STMPE24XX_REG_SYS_CTRL2, > [STMPE_IDX_ICR_LSB] = STMPE24XX_REG_ICR_LSB, > [STMPE_IDX_IER_LSB] = STMPE24XX_REG_IER_LSB, > [STMPE_IDX_ISR_MSB] = STMPE24XX_REG_ISR_MSB, > @@ -819,7 +826,7 @@ static int stmpe24xx_enable(struct stmpe *stmpe, unsigned int blocks, > if (blocks & STMPE_BLOCK_KEYPAD) > mask |= STMPE24XX_SYS_CTRL_ENABLE_KPC; > > - return __stmpe_set_bits(stmpe, STMPE24XX_REG_SYS_CTRL, mask, > + return __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL], mask, > enable ? mask : 0); > } > > diff --git a/drivers/mfd/stmpe.h b/drivers/mfd/stmpe.h > index 84adb46..406f9f2 100644 > --- a/drivers/mfd/stmpe.h > +++ b/drivers/mfd/stmpe.h > @@ -138,6 +138,7 @@ int stmpe_remove(struct stmpe *stmpe); > #define STMPE811_NR_INTERNAL_IRQS 8 > > #define STMPE811_REG_CHIP_ID 0x00 > +#define STMPE811_REG_SYS_CTRL 0x03 > #define STMPE811_REG_SYS_CTRL2 0x04 > #define STMPE811_REG_SPI_CFG 0x08 > #define STMPE811_REG_INT_CTRL 0x09 > @@ -264,6 +265,7 @@ int stmpe_remove(struct stmpe *stmpe); > #define STMPE24XX_NR_INTERNAL_IRQS 9 > > #define STMPE24XX_REG_SYS_CTRL 0x02 > +#define STMPE24XX_REG_SYS_CTRL2 0x03 > #define STMPE24XX_REG_ICR_LSB 0x11 > #define STMPE24XX_REG_IER_LSB 0x13 > #define STMPE24XX_REG_ISR_MSB 0x14 > diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h > index cb83883..6c6690f 100644 > --- a/include/linux/mfd/stmpe.h > +++ b/include/linux/mfd/stmpe.h > @@ -39,6 +39,8 @@ enum stmpe_partnum { > */ > enum { > STMPE_IDX_CHIP_ID, > + STMPE_IDX_SYS_CTRL, > + STMPE_IDX_SYS_CTRL2, > STMPE_IDX_ICR_LSB, > STMPE_IDX_IER_LSB, > STMPE_IDX_ISR_LSB, -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog