From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v11 1/7] drm/i915/gen6+: Return -EINVAL on invalid pcode commands Date: Fri, 12 Aug 2016 14:23:28 +0300 Message-ID: <20160812112328.GX4329@intel.com> References: <1470945277-7973-1-git-send-email-cpaul@redhat.com> <1470945277-7973-2-git-send-email-cpaul@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1470945277-7973-2-git-send-email-cpaul@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Lyude Cc: dri-devel@lists.freedesktop.org, David Airlie , Daniel Vetter , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Daniel Vetter List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBBdWcgMTEsIDIwMTYgYXQgMDM6NTQ6MzBQTSAtMDQwMCwgTHl1ZGUgd3JvdGU6Cj4g SW4gb3JkZXIgdG8gYWRkIHByb3BlciBzdXBwb3J0IGZvciB0aGUgU0FHViwgd2UgbmVlZCB0byBi ZSBhYmxlIHRvIGtub3cKPiB3aGF0IHRoZSBjYXVzZSBvZiBhIGZhaWx1cmUgdG8gY2hhbmdlIHRo ZSBTQUdWIHRocm91Z2ggdGhlIHBjb2RlIG1haWxib3gKPiB3YXMuIFRoZSByZWFzb25pbmcgZm9y IHRoaXMgaXMgdGhhdCBzb21lIHZlcnkgZWFybHkgcHJlLXJlbGVhc2UgU2t5bGFrZQo+IG1hY2hp bmVzIGRvbid0IGFjdHVhbGx5IGFsbG93IHlvdSB0byBjb250cm9sIHRoZSBTQUdWIG9uIHRoZW0s IGFuZAo+IGluZGljYXRlIGFuIGludmFsaWQgbWFpbGJveCBjb21tYW5kIHdhcyBzZW50Lgo+IAo+ IFRoaXMgYWxzbyBtaWdodCBjb21lIGluIGhhbmR5IGluIHRoZSBmdXR1cmUgZm9yIGRlYnVnZ2lu Zy4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBMeXVkZSA8Y3BhdWxAcmVkaGF0LmNvbT4KPiBDYzogTWF0 dCBSb3BlciA8bWF0dGhldy5kLnJvcGVyQGludGVsLmNvbT4KPiBDYzogTWFhcnRlbiBMYW5raG9y c3QgPG1hYXJ0ZW4ubGFua2hvcnN0QGxpbnV4LmludGVsLmNvbT4KPiBDYzogRGFuaWVsIFZldHRl ciA8ZGFuaWVsLnZldHRlckBmZndsbC5jaD4KPiBDYzogVmlsbGUgU3lyasOkbMOkIDx2aWxsZS5z eXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPiBDYzogc3RhYmxlQHZnZXIua2VybmVsLm9yZwo+IC0t LQo+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oIHwgIDEgKwo+ICBkcml2ZXJzL2dw dS9kcm0vaTkxNS9pbnRlbF9wbS5jIHwgMTAgKysrKysrKysrKwo+ICAyIGZpbGVzIGNoYW5nZWQs IDExIGluc2VydGlvbnMoKykKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUv aTkxNV9yZWcuaCBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgKPiBpbmRleCBkYTgy NzQ0Li43M2IzZDRkIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVn LmgKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oCj4gQEAgLTcxMjEsNiAr NzEyMSw3IEBAIGVudW0gewo+ICAjZGVmaW5lIFZMVl9NRURJQV9DMF9DT1VOVAkJCV9NTUlPKDB4 MTM4MTFDKQo+ICAKPiAgI2RlZmluZSBHRU42X1BDT0RFX01BSUxCT1gJCQlfTU1JTygweDEzODEy NCkKPiArI2RlZmluZSAgIEdFTjZfUENPREVfSU5WQUxJRF9DTUQJCSgxPDwwKQoKSXQgZG9lc24n dCB3b3JrIHF1aXRlIGxpa2UgdGhhdC4gSW5zdGVhZCB0aGUgbG93IDggYml0cyB3aWxsIGNvbnRp YW4KdGhlIGVycm9yIGNvZGUsIGlmZiBwY29kZSBoYXMgY2xlYXJlZCB0aGUgIlJFQURZIiBiaXQ6 CgpzbmItaXZiIGRvY3Mgc2F5OgowMGggTUFJTEJPWF9HVERSSVZFUl9DQ19TVUNDRVNTCjAxaCBN QUlMQk9YX0dURFJJVkVSX0NDX0lMTEVHQUxfQ01ECjAyaCBNQUlMQk9YX0dURFJJVkVSX0NDX01J Tl9GUkVRVUVOQ1lfVEFCTEVfR1RfUkFUSU9fT1VUX09GX1JBTkdFCjAzaCBNQUlMQk9YX0dURFJJ VkVSX0NDX1RJTUVPVVQKRkZoIE1BSUxCT1hfR1REUklWRVJfQ0NfVU5JTVBMRU1FTlRFRF9DTUQK Cmhzdy1iZHcgZG9jcyBzYXk6CjAwaCBTVUNDRVNTCjAxaCBJTExFR0FMX0NNRAowMmggVElNRU9V VAowM2ggSUxMRUdBTF9EQVRBCjEwaCBNSU5fRlJFUVVFTkNZX1RBQkxFX0dUX1JBVElPX09VVF9P Rl9SQU5HRQoKc2tsIGRvY3Mgc2F5OgowMGggU1VDQ0VTUwowMWggSUxMRUdBTF9DTUQKMDJoIFRJ TUVPVVQKMDNoIElMTEVHQUxfREFUQQoKU28gbG9va3MgbGlrZSAwMmggYW5kIDAzaCB3aWxsIG5l ZWQgdG8gYmUgaW50ZXJwcmV0ZWQgaW4gdHdvIGRpZmZlcmVudAp3YXlzIGRlcGVuZGluZyBvbiB0 aGUgcGxhdGZvcm0uIEFzc3VtaW5nIHdlIHdhbnQgdG8gZGVjb2RlIHRoZSBlcnJvcgppbnRvIGEg YSBodW1hbiByZWFkYWJsZSBmb3JtIGZvciBkbWVzZy4KCj4gICNkZWZpbmUgICBHRU42X1BDT0RF X1JFQURZCQkJKDE8PDMxKQo+ICAjZGVmaW5lCSAgR0VONl9QQ09ERV9XUklURV9SQzZWSURTCQkw eDQKPiAgI2RlZmluZQkgIEdFTjZfUENPREVfUkVBRF9SQzZWSURTCQkweDUKPiBkaWZmIC0tZ2l0 IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfcG0uYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2ludGVsX3BtLmMKPiBpbmRleCA5OTAxNGQ3Li44NzUyNzMwIDEwMDY0NAo+IC0tLSBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX3BtLmMKPiArKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9p bnRlbF9wbS5jCj4gQEAgLTc2NzQsNiArNzY3NCwxMSBAQCBpbnQgc2FuZHlicmlkZ2VfcGNvZGVf cmVhZChzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsIHUzMiBtYm94LCB1MzIgKnZh bAo+ICAJKnZhbCA9IEk5MTVfUkVBRF9GVyhHRU42X1BDT0RFX0RBVEEpOwo+ICAJSTkxNV9XUklU RV9GVyhHRU42X1BDT0RFX0RBVEEsIDApOwo+ICAKPiArCWlmIChJOTE1X1JFQURfRlcoR0VONl9Q Q09ERV9NQUlMQk9YKSAmIEdFTjZfUENPREVfSU5WQUxJRF9DTUQpIHsKPiArCQlEUk1fREVCVUdf RFJJVkVSKCJ3YXJuaW5nOiBwY29kZSAocmVhZCkgbWFpbGJveCBhY2Nlc3MgaW5kaWNhdGVkIGlu dmFsaWQgY29tbWFuZFxuIik7Cj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwl9Cj4gKwo+ICAJcmV0 dXJuIDA7Cj4gIH0KPiAgCj4gQEAgLTc3MDQsNiArNzcwOSwxMSBAQCBpbnQgc2FuZHlicmlkZ2Vf cGNvZGVfd3JpdGUoc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2LAo+ICAKPiAgCUk5 MTVfV1JJVEVfRlcoR0VONl9QQ09ERV9EQVRBLCAwKTsKPiAgCj4gKwlpZiAoSTkxNV9SRUFEX0ZX KEdFTjZfUENPREVfTUFJTEJPWCkgJiBHRU42X1BDT0RFX0lOVkFMSURfQ01EKSB7Cj4gKwkJRFJN X0RFQlVHX0RSSVZFUigid2FybmluZzogcGNvZGUgKHdyaXRlKSBtYWlsYm94IGFjY2VzcyBpbmRp Y2F0ZWQgaW52YWxpZCBjb21tYW5kXG4iKTsKPiArCQlyZXR1cm4gLUVJTlZBTDsKPiArCX0KPiAr Cj4gIAlyZXR1cm4gMDsKPiAgfQo+ICAKPiAtLSAKPiAyLjcuNAoKLS0gClZpbGxlIFN5cmrDpGzD pApJbnRlbCBPVEMKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752296AbcHLLXj (ORCPT ); Fri, 12 Aug 2016 07:23:39 -0400 Received: from mga09.intel.com ([134.134.136.24]:60301 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753162AbcHLLXf (ORCPT ); Fri, 12 Aug 2016 07:23:35 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,510,1464678000"; d="scan'208";a="1024289279" Date: Fri, 12 Aug 2016 14:23:28 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Lyude Cc: intel-gfx@lists.freedesktop.org, Maarten Lankhorst , Matt Roper , Daniel Vetter , stable@vger.kernel.org, Daniel Vetter , Jani Nikula , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v11 1/7] drm/i915/gen6+: Return -EINVAL on invalid pcode commands Message-ID: <20160812112328.GX4329@intel.com> References: <1470945277-7973-1-git-send-email-cpaul@redhat.com> <1470945277-7973-2-git-send-email-cpaul@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1470945277-7973-2-git-send-email-cpaul@redhat.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 11, 2016 at 03:54:30PM -0400, Lyude wrote: > In order to add proper support for the SAGV, we need to be able to know > what the cause of a failure to change the SAGV through the pcode mailbox > was. The reasoning for this is that some very early pre-release Skylake > machines don't actually allow you to control the SAGV on them, and > indicate an invalid mailbox command was sent. > > This also might come in handy in the future for debugging. > > Signed-off-by: Lyude > Cc: Matt Roper > Cc: Maarten Lankhorst > Cc: Daniel Vetter > Cc: Ville Syrjälä > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index da82744..73b3d4d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7121,6 +7121,7 @@ enum { > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) > > #define GEN6_PCODE_MAILBOX _MMIO(0x138124) > +#define GEN6_PCODE_INVALID_CMD (1<<0) It doesn't work quite like that. Instead the low 8 bits will contian the error code, iff pcode has cleared the "READY" bit: snb-ivb docs say: 00h MAILBOX_GTDRIVER_CC_SUCCESS 01h MAILBOX_GTDRIVER_CC_ILLEGAL_CMD 02h MAILBOX_GTDRIVER_CC_MIN_FREQUENCY_TABLE_GT_RATIO_OUT_OF_RANGE 03h MAILBOX_GTDRIVER_CC_TIMEOUT FFh MAILBOX_GTDRIVER_CC_UNIMPLEMENTED_CMD hsw-bdw docs say: 00h SUCCESS 01h ILLEGAL_CMD 02h TIMEOUT 03h ILLEGAL_DATA 10h MIN_FREQUENCY_TABLE_GT_RATIO_OUT_OF_RANGE skl docs say: 00h SUCCESS 01h ILLEGAL_CMD 02h TIMEOUT 03h ILLEGAL_DATA So looks like 02h and 03h will need to be interpreted in two different ways depending on the platform. Assuming we want to decode the error into a a human readable form for dmesg. > #define GEN6_PCODE_READY (1<<31) > #define GEN6_PCODE_WRITE_RC6VIDS 0x4 > #define GEN6_PCODE_READ_RC6VIDS 0x5 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 99014d7..8752730 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7674,6 +7674,11 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val > *val = I915_READ_FW(GEN6_PCODE_DATA); > I915_WRITE_FW(GEN6_PCODE_DATA, 0); > > + if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_INVALID_CMD) { > + DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access indicated invalid command\n"); > + return -EINVAL; > + } > + > return 0; > } > > @@ -7704,6 +7709,11 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, > > I915_WRITE_FW(GEN6_PCODE_DATA, 0); > > + if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_INVALID_CMD) { > + DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access indicated invalid command\n"); > + return -EINVAL; > + } > + > return 0; > } > > -- > 2.7.4 -- Ville Syrjälä Intel OTC From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Fri, 12 Aug 2016 14:23:28 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Lyude Cc: intel-gfx@lists.freedesktop.org, Maarten Lankhorst , Matt Roper , Daniel Vetter , stable@vger.kernel.org, Daniel Vetter , Jani Nikula , David Airlie , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v11 1/7] drm/i915/gen6+: Return -EINVAL on invalid pcode commands Message-ID: <20160812112328.GX4329@intel.com> References: <1470945277-7973-1-git-send-email-cpaul@redhat.com> <1470945277-7973-2-git-send-email-cpaul@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1470945277-7973-2-git-send-email-cpaul@redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: On Thu, Aug 11, 2016 at 03:54:30PM -0400, Lyude wrote: > In order to add proper support for the SAGV, we need to be able to know > what the cause of a failure to change the SAGV through the pcode mailbox > was. The reasoning for this is that some very early pre-release Skylake > machines don't actually allow you to control the SAGV on them, and > indicate an invalid mailbox command was sent. > > This also might come in handy in the future for debugging. > > Signed-off-by: Lyude > Cc: Matt Roper > Cc: Maarten Lankhorst > Cc: Daniel Vetter > Cc: Ville Syrj�l� > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index da82744..73b3d4d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7121,6 +7121,7 @@ enum { > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) > > #define GEN6_PCODE_MAILBOX _MMIO(0x138124) > +#define GEN6_PCODE_INVALID_CMD (1<<0) It doesn't work quite like that. Instead the low 8 bits will contian the error code, iff pcode has cleared the "READY" bit: snb-ivb docs say: 00h MAILBOX_GTDRIVER_CC_SUCCESS 01h MAILBOX_GTDRIVER_CC_ILLEGAL_CMD 02h MAILBOX_GTDRIVER_CC_MIN_FREQUENCY_TABLE_GT_RATIO_OUT_OF_RANGE 03h MAILBOX_GTDRIVER_CC_TIMEOUT FFh MAILBOX_GTDRIVER_CC_UNIMPLEMENTED_CMD hsw-bdw docs say: 00h SUCCESS 01h ILLEGAL_CMD 02h TIMEOUT 03h ILLEGAL_DATA 10h MIN_FREQUENCY_TABLE_GT_RATIO_OUT_OF_RANGE skl docs say: 00h SUCCESS 01h ILLEGAL_CMD 02h TIMEOUT 03h ILLEGAL_DATA So looks like 02h and 03h will need to be interpreted in two different ways depending on the platform. Assuming we want to decode the error into a a human readable form for dmesg. > #define GEN6_PCODE_READY (1<<31) > #define GEN6_PCODE_WRITE_RC6VIDS 0x4 > #define GEN6_PCODE_READ_RC6VIDS 0x5 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 99014d7..8752730 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7674,6 +7674,11 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val > *val = I915_READ_FW(GEN6_PCODE_DATA); > I915_WRITE_FW(GEN6_PCODE_DATA, 0); > > + if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_INVALID_CMD) { > + DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access indicated invalid command\n"); > + return -EINVAL; > + } > + > return 0; > } > > @@ -7704,6 +7709,11 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, > > I915_WRITE_FW(GEN6_PCODE_DATA, 0); > > + if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_INVALID_CMD) { > + DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access indicated invalid command\n"); > + return -EINVAL; > + } > + > return 0; > } > > -- > 2.7.4 -- Ville Syrj�l� Intel OTC