diff for duplicates of <20160818180840.GE361@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 3d168f1..09a4934 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -24,7 +24,7 @@ What's this interrupt for? 0x304 seems wrong as well, because 0x3 would mean two CPUs and this is a SPI and not a PPI? > + -> + cpu0: cpu@0 { +> + cpu0: cpu at 0 { > + compatible = "arm,cortex-a5"; > + device_type = "cpu"; > + next-level-cache = <&L2>; @@ -62,7 +62,7 @@ This is unnecessary as it's the same name as the node name. > + cache-level = <2>; > + }; > + -> + intc: interrupt-controller@2000000 { +> + intc: interrupt-controller at 2000000 { > + compatible = "qcom,msm-qgic2"; > + interrupt-controller; > + #interrupt-cells = <3>; @@ -70,7 +70,7 @@ This is unnecessary as it's the same name as the node name. > + <0x02002000 0x1000>; > + }; > + -> + timer@200a000 { +> + timer at 200a000 { > + compatible = "qcom,kpss-timer", "qcom,msm-timer"; > + interrupts = <GIC_PPI 1 0x301>, > + <GIC_PPI 2 0x301>, @@ -84,7 +84,7 @@ This is unnecessary as it's the same name as the node name. > + cpu-offset = <0x80000>; > + }; > + -> + msmgpio: pinctrl@800000 { +> + msmgpio: pinctrl at 800000 { > + compatible = "qcom,mdm9615-pinctrl", "syscon"; What's the syscon for? @@ -97,26 +97,26 @@ What's the syscon for? > + reg = <0x800000 0x4000>; > + }; > + -> + gcc: clock-controller@900000 { +> + gcc: clock-controller at 900000 { > + compatible = "qcom,gcc-mdm9615"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + reg = <0x900000 0x4000>; > + }; > + -> + lcc: clock-controller@28000000 { +> + lcc: clock-controller at 28000000 { > + compatible = "qcom,lcc-mdm9615"; > + reg = <0x28000000 0x1000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + -> + l2cc: clock-controller@2011000 { +> + l2cc: clock-controller at 2011000 { > + compatible = "syscon"; > + reg = <0x02011000 0x1000>; > + }; > + -> + rng@1a500000 { +> + rng at 1a500000 { > + compatible = "qcom,prng"; > + reg = <0x1a500000 0x200>; > + clocks = <&gcc PRNG_CLK>; @@ -136,7 +136,7 @@ What's the syscon for? This should go into the root under a "regulators" node. > + -> + gsbi2: gsbi@16100000 { +> + gsbi2: gsbi at 16100000 { > + compatible = "qcom,gsbi-v1.0.0"; > + cell-index = <2>; > + reg = <0x16100000 0x100>; @@ -147,7 +147,7 @@ This should go into the root under a "regulators" node. > + #size-cells = <1>; > + ranges; > + -> + gsbi2_i2c: i2c@16180000 { +> + gsbi2_i2c: i2c at 16180000 { > + compatible = "qcom,i2c-qup-v1.1.1"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -163,7 +163,7 @@ There should be a trigger type... high perhaps? > + }; > + }; > + -> + gsbi3: gsbi@16200000 { +> + gsbi3: gsbi at 16200000 { > + compatible = "qcom,gsbi-v1.0.0"; > + cell-index = <3>; > + reg = <0x16200000 0x100>; @@ -174,7 +174,7 @@ There should be a trigger type... high perhaps? > + #size-cells = <1>; > + ranges; > + -> + gsbi3_spi: spi@16280000 { +> + gsbi3_spi: spi at 16280000 { > + compatible = "qcom,spi-qup-v1.1.1"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -188,7 +188,7 @@ There should be a trigger type... high perhaps? > + }; > + }; > + -> + gsbi4: gsbi@16300000 { +> + gsbi4: gsbi at 16300000 { > + compatible = "qcom,gsbi-v1.0.0"; > + cell-index = <4>; > + reg = <0x16300000 0x100>; @@ -201,7 +201,7 @@ There should be a trigger type... high perhaps? > + > + syscon-tcsr = <&tcsr>; > + -> + gsbi4_serial: serial@16340000 { +> + gsbi4_serial: serial at 16340000 { > + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; > + reg = <0x16340000 0x1000>, > + <0x16300000 0x1000>; @@ -212,7 +212,7 @@ There should be a trigger type... high perhaps? > + }; > + }; > + -> + gsbi5: gsbi@16400000 { +> + gsbi5: gsbi at 16400000 { > + compatible = "qcom,gsbi-v1.0.0"; > + cell-index = <5>; > + reg = <0x16400000 0x100>; @@ -225,7 +225,7 @@ There should be a trigger type... high perhaps? > + > + syscon-tcsr = <&tcsr>; > + -> + gsbi5_i2c: i2c@16480000 { +> + gsbi5_i2c: i2c at 16480000 { > + compatible = "qcom,i2c-qup-v1.1.1"; > + #address-cells = <1>; > + #size-cells = <0>; @@ -241,7 +241,7 @@ There should be a trigger type... high perhaps? > + status = "disabled"; > + }; > + -> + gsbi5_serial: serial@16440000 { +> + gsbi5_serial: serial at 16440000 { > + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; > + reg = <0x16440000 0x1000>, > + <0x16400000 0x1000>; @@ -252,12 +252,12 @@ There should be a trigger type... high perhaps? > + }; > + }; > + -> + qcom,ssbi@500000 { +> + qcom,ssbi at 500000 { > + compatible = "qcom,ssbi"; > + reg = <0x500000 0x1000>; > + qcom,controller-type = "pmic-arbiter"; > + -> + pmicintc: pmic@0 { +> + pmicintc: pmic at 0 { > + compatible = "qcom,pm8018", "qcom,pm8921"; I know that DT specifies most specific compatible first, but when @@ -274,7 +274,7 @@ Can we have interrupt-parent = <&pmicintc> here instead of in every node? > + -> + pwrkey@1c { +> + pwrkey at 1c { > + compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey"; > + reg = <0x1c>; > + interrupt-parent = <&pmicintc>; @@ -284,7 +284,7 @@ every node? > + pull-up; > + }; > + -> + pmicmpp: mpp@50 { +> + pmicmpp: mpp at 50 { > + compatible = "qcom,pm8018-mpp"; > + interrupt-parent = <&pmicintc>; > + interrupts = <24 IRQ_TYPE_EDGE_RISING>, @@ -301,7 +301,7 @@ We've recently been reminded that these should all be IRQ_TYPE_NONE. Also add th > + #gpio-cells = <2>; > + }; > + -> + rtc@11d { +> + rtc at 11d { > + compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc"; > + interrupt-parent = <&pmicintc>; > + interrupts = <39 IRQ_TYPE_EDGE_RISING>; @@ -309,7 +309,7 @@ We've recently been reminded that these should all be IRQ_TYPE_NONE. Also add th > + allow-set-time; > + }; > + -> + pmicgpio: gpio@150 { +> + pmicgpio: gpio at 150 { > + compatible = "qcom,pm8018-gpio"; > + interrupt-parent = <&pmicintc>; > + interrupts = <24 IRQ_TYPE_EDGE_RISING>, @@ -328,11 +328,11 @@ compatible please. > + }; > + }; > + -> + sdcc1bam:dma@12182000{ +> + sdcc1bam:dma at 12182000{ Add some space here: - sdcc1bam: dma@12180000 { + sdcc1bam: dma at 12180000 { > + compatible = "qcom,bam-v1.3.0"; > + reg = <0x12182000 0x8000>; @@ -343,7 +343,7 @@ Add some space here: > + qcom,ee = <0>; > + }; > + -> + sdcc2bam:dma@12142000{ +> + sdcc2bam:dma at 12142000{ ditto. diff --git a/a/content_digest b/N1/content_digest index 73c440e..4c1368d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,9 @@ "ref\01471525661-2563-1-git-send-email-narmstrong@baylibre.com\0" "ref\01471525661-2563-2-git-send-email-narmstrong@baylibre.com\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" - "Subject\0Re: [PATCH v2 1/2] ARM: dts: Add MDM9615 dtsi\0" + "From\0sboyd@codeaurora.org (Stephen Boyd)\0" + "Subject\0[PATCH v2 1/2] ARM: dts: Add MDM9615 dtsi\0" "Date\0Thu, 18 Aug 2016 11:08:40 -0700\0" - "To\0Neil Armstrong <narmstrong@baylibre.com>\0" - "Cc\0devicetree@vger.kernel.org" - linux-arm-msm@vger.kernel.org - linux@armlinux.org.uk - linux-kernel@vger.kernel.org - david.brown@linaro.org - andy.gross@linaro.org - linux-soc@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 08/18, Neil Armstrong wrote:\n" @@ -40,7 +32,7 @@ "would mean two CPUs and this is a SPI and not a PPI?\n" "\n" "> +\n" - "> +\t\tcpu0: cpu@0 {\n" + "> +\t\tcpu0: cpu at 0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a5\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tnext-level-cache = <&L2>;\n" @@ -78,7 +70,7 @@ "> +\t\t\tcache-level = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tintc: interrupt-controller@2000000 {\n" + "> +\t\tintc: interrupt-controller at 2000000 {\n" "> +\t\t\tcompatible = \"qcom,msm-qgic2\";\n" "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <3>;\n" @@ -86,7 +78,7 @@ "> +\t\t\t <0x02002000 0x1000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ttimer@200a000 {\n" + "> +\t\ttimer at 200a000 {\n" "> +\t\t\tcompatible = \"qcom,kpss-timer\", \"qcom,msm-timer\";\n" "> +\t\t\tinterrupts = <GIC_PPI 1 0x301>,\n" "> +\t\t\t\t <GIC_PPI 2 0x301>,\n" @@ -100,7 +92,7 @@ "> +\t\t\tcpu-offset = <0x80000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmsmgpio: pinctrl@800000 {\n" + "> +\t\tmsmgpio: pinctrl at 800000 {\n" "> +\t\t\tcompatible = \"qcom,mdm9615-pinctrl\", \"syscon\";\n" "\n" "What's the syscon for?\n" @@ -113,26 +105,26 @@ "> +\t\t\treg = <0x800000 0x4000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgcc: clock-controller@900000 {\n" + "> +\t\tgcc: clock-controller at 900000 {\n" "> +\t\t\tcompatible = \"qcom,gcc-mdm9615\";\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\treg = <0x900000 0x4000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlcc: clock-controller@28000000 {\n" + "> +\t\tlcc: clock-controller at 28000000 {\n" "> +\t\t\tcompatible = \"qcom,lcc-mdm9615\";\n" "> +\t\t\treg = <0x28000000 0x1000>;\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tl2cc: clock-controller@2011000 {\n" + "> +\t\tl2cc: clock-controller at 2011000 {\n" "> +\t\t\tcompatible = \"syscon\";\n" "> +\t\t\treg = <0x02011000 0x1000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\trng@1a500000 {\n" + "> +\t\trng at 1a500000 {\n" "> +\t\t\tcompatible = \"qcom,prng\";\n" "> +\t\t\treg = <0x1a500000 0x200>;\n" "> +\t\t\tclocks = <&gcc PRNG_CLK>;\n" @@ -152,7 +144,7 @@ "This should go into the root under a \"regulators\" node.\n" "\n" "> +\n" - "> +\t\tgsbi2: gsbi@16100000 {\n" + "> +\t\tgsbi2: gsbi at 16100000 {\n" "> +\t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n" "> +\t\t\tcell-index = <2>;\n" "> +\t\t\treg = <0x16100000 0x100>;\n" @@ -163,7 +155,7 @@ "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges;\n" "> +\n" - "> +\t\t\tgsbi2_i2c: i2c@16180000 {\n" + "> +\t\t\tgsbi2_i2c: i2c at 16180000 {\n" "> +\t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n" "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" @@ -179,7 +171,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tgsbi3: gsbi@16200000 {\n" + "> +\t\tgsbi3: gsbi at 16200000 {\n" "> +\t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n" "> +\t\t\tcell-index = <3>;\n" "> +\t\t\treg = <0x16200000 0x100>;\n" @@ -190,7 +182,7 @@ "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges;\n" "> +\n" - "> +\t\t\tgsbi3_spi: spi@16280000 {\n" + "> +\t\t\tgsbi3_spi: spi at 16280000 {\n" "> +\t\t\t\tcompatible = \"qcom,spi-qup-v1.1.1\";\n" "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" @@ -204,7 +196,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tgsbi4: gsbi@16300000 {\n" + "> +\t\tgsbi4: gsbi at 16300000 {\n" "> +\t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n" "> +\t\t\tcell-index = <4>;\n" "> +\t\t\treg = <0x16300000 0x100>;\n" @@ -217,7 +209,7 @@ "> +\n" "> +\t\t\tsyscon-tcsr = <&tcsr>;\n" "> +\n" - "> +\t\t\tgsbi4_serial: serial@16340000 {\n" + "> +\t\t\tgsbi4_serial: serial at 16340000 {\n" "> +\t\t\t\tcompatible = \"qcom,msm-uartdm-v1.3\", \"qcom,msm-uartdm\";\n" "> +\t\t\t\treg = <0x16340000 0x1000>,\n" "> +\t\t\t\t <0x16300000 0x1000>;\n" @@ -228,7 +220,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tgsbi5: gsbi@16400000 {\n" + "> +\t\tgsbi5: gsbi at 16400000 {\n" "> +\t\t\tcompatible = \"qcom,gsbi-v1.0.0\";\n" "> +\t\t\tcell-index = <5>;\n" "> +\t\t\treg = <0x16400000 0x100>;\n" @@ -241,7 +233,7 @@ "> +\n" "> +\t\t\tsyscon-tcsr = <&tcsr>;\n" "> +\n" - "> +\t\t\tgsbi5_i2c: i2c@16480000 {\n" + "> +\t\t\tgsbi5_i2c: i2c at 16480000 {\n" "> +\t\t\t\tcompatible = \"qcom,i2c-qup-v1.1.1\";\n" "> +\t\t\t\t#address-cells = <1>;\n" "> +\t\t\t\t#size-cells = <0>;\n" @@ -257,7 +249,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tgsbi5_serial: serial@16440000 {\n" + "> +\t\t\tgsbi5_serial: serial at 16440000 {\n" "> +\t\t\t\tcompatible = \"qcom,msm-uartdm-v1.3\", \"qcom,msm-uartdm\";\n" "> +\t\t\t\treg = <0x16440000 0x1000>,\n" "> +\t\t\t\t <0x16400000 0x1000>;\n" @@ -268,12 +260,12 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tqcom,ssbi@500000 {\n" + "> +\t\tqcom,ssbi at 500000 {\n" "> +\t\t\tcompatible = \"qcom,ssbi\";\n" "> +\t\t\treg = <0x500000 0x1000>;\n" "> +\t\t\tqcom,controller-type = \"pmic-arbiter\";\n" "> +\n" - "> +\t\t\tpmicintc: pmic@0 {\n" + "> +\t\t\tpmicintc: pmic at 0 {\n" "> +\t\t\t\tcompatible = \"qcom,pm8018\", \"qcom,pm8921\";\n" "\n" "I know that DT specifies most specific compatible first, but when\n" @@ -290,7 +282,7 @@ "every node?\n" "\n" "> +\n" - "> +\t\t\t\tpwrkey@1c {\n" + "> +\t\t\t\tpwrkey at 1c {\n" "> +\t\t\t\t\tcompatible = \"qcom,pm8018-pwrkey\", \"qcom,pm8921-pwrkey\";\n" "> +\t\t\t\t\treg = <0x1c>;\n" "> +\t\t\t\t\tinterrupt-parent = <&pmicintc>;\n" @@ -300,7 +292,7 @@ "> +\t\t\t\t\tpull-up;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpmicmpp: mpp@50 {\n" + "> +\t\t\t\tpmicmpp: mpp at 50 {\n" "> +\t\t\t\t\tcompatible = \"qcom,pm8018-mpp\";\n" "> +\t\t\t\t\tinterrupt-parent = <&pmicintc>;\n" "> +\t\t\t\t\tinterrupts = <24 IRQ_TYPE_EDGE_RISING>,\n" @@ -317,7 +309,7 @@ "> +\t\t\t\t\t#gpio-cells = <2>;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\trtc@11d {\n" + "> +\t\t\t\trtc at 11d {\n" "> +\t\t\t\t\tcompatible = \"qcom,pm8018-rtc\", \"qcom,pm8921-rtc\";\n" "> +\t\t\t\t\tinterrupt-parent = <&pmicintc>;\n" "> +\t\t\t\t\tinterrupts = <39 IRQ_TYPE_EDGE_RISING>;\n" @@ -325,7 +317,7 @@ "> +\t\t\t\t\tallow-set-time;\n" "> +\t\t\t\t};\n" "> +\n" - "> +\t\t\t\tpmicgpio: gpio@150 {\n" + "> +\t\t\t\tpmicgpio: gpio at 150 {\n" "> +\t\t\t\t\tcompatible = \"qcom,pm8018-gpio\";\n" "> +\t\t\t\t\tinterrupt-parent = <&pmicintc>;\n" "> +\t\t\t\t\tinterrupts = <24 IRQ_TYPE_EDGE_RISING>,\n" @@ -344,11 +336,11 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tsdcc1bam:dma@12182000{\n" + "> +\t\tsdcc1bam:dma at 12182000{\n" "\n" "Add some space here:\n" "\n" - "\t\tsdcc1bam: dma@12180000 {\n" + "\t\tsdcc1bam: dma at 12180000 {\n" "\n" "> +\t\t\tcompatible = \"qcom,bam-v1.3.0\";\n" "> +\t\t\treg = <0x12182000 0x8000>;\n" @@ -359,7 +351,7 @@ "> +\t\t\tqcom,ee = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tsdcc2bam:dma@12142000{\n" + "> +\t\tsdcc2bam:dma at 12142000{\n" "\n" "ditto.\n" "\n" @@ -380,4 +372,4 @@ "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" a Linux Foundation Collaborative Project -6f7050745a950685beeddf96d8a254833723757992e2aad3b07e1d76faff770f +053a29fd4d3b64ba31119202d3d00c8621b8c5f7d15c2dacfc16fd2b4f6332b9
diff --git a/a/content_digest b/N2/content_digest index 73c440e..99ddff6 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -4,12 +4,12 @@ "Subject\0Re: [PATCH v2 1/2] ARM: dts: Add MDM9615 dtsi\0" "Date\0Thu, 18 Aug 2016 11:08:40 -0700\0" "To\0Neil Armstrong <narmstrong@baylibre.com>\0" - "Cc\0devicetree@vger.kernel.org" - linux-arm-msm@vger.kernel.org + "Cc\0andy.gross@linaro.org" + david.brown@linaro.org linux@armlinux.org.uk + devicetree@vger.kernel.org linux-kernel@vger.kernel.org - david.brown@linaro.org - andy.gross@linaro.org + linux-arm-msm@vger.kernel.org linux-soc@vger.kernel.org " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" @@ -380,4 +380,4 @@ "Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,\n" a Linux Foundation Collaborative Project -6f7050745a950685beeddf96d8a254833723757992e2aad3b07e1d76faff770f +76c4298edea0be4a1e8c8a10aa9c16c52ea5e4e24cb61caed6fb64ac71089ee7
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