Re: [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4

[no-reply@patchew.org]

Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1473662506-27441-1-git-send-email-nikunj@linux.vnet.ibm.com
Subject: [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
bd71c6f target-ppc: add stxvb16x and stxvh8x
bb4334f target-ppc: improve stxvw4x implementation
dcd12d2 target-ppc: add lxvb16x and lxvh8x
623b945 target-ppc: improve lxvw4x implementation
165f015 target-ppc: add stxsi[bh]x instruction
2c19405 target-ppc: add lxsi[bw]zx instruction
b83a0fa target-ppc: implement darn instruction
2983841 target-ppc: add xxspltib instruction
45d1faf target-ppc: consolidate store conditional
4d12515 target-ppc: move out stqcx impementation
d937588 target-ppc: consolidate load with reservation
da405fb target-ppc: convert st[16, 32, 64]r to use new macro
6df6f91 target-ppc: convert st64 to use new macro
0033af2 target-ppc: consolidate store operations
c74871d target-ppc: convert ld[16, 32, 64]ur to use new macro
cafa0ef target-ppc: convert ld64 to use new macro
cd34c15 target-ppc: consolidate load operations

=== OUTPUT BEGIN ===
Checking PATCH 1/17: target-ppc: consolidate load operations...
Checking PATCH 2/17: target-ppc: convert ld64 to use new macro...
Checking PATCH 3/17: target-ppc: convert ld[16, 32, 64]ur to use new macro...
Checking PATCH 4/17: target-ppc: consolidate store operations...
Checking PATCH 5/17: target-ppc: convert st64 to use new macro...
Checking PATCH 6/17: target-ppc: convert st[16, 32, 64]r to use new macro...
Checking PATCH 7/17: target-ppc: consolidate load with reservation...
Checking PATCH 8/17: target-ppc: move out stqcx impementation...
Checking PATCH 9/17: target-ppc: consolidate store conditional...
Checking PATCH 10/17: target-ppc: add xxspltib instruction...
ERROR: Macros with complex values should be enclosed in parenthesis
#65: FILE: target-ppc/translate/vsx-ops.inc.c:23:
+#define GEN_XX1FORM(name, opc2, opc3, fl2)                              \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)

total: 1 errors, 0 warnings, 51 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 11/17: target-ppc: implement darn instruction...
Checking PATCH 12/17: target-ppc: add lxsi[bw]zx instruction...
Checking PATCH 13/17: target-ppc: add stxsi[bh]x instruction...
Checking PATCH 14/17: target-ppc: improve lxvw4x implementation...
Checking PATCH 15/17: target-ppc: add lxvb16x and lxvh8x...
Checking PATCH 16/17: target-ppc: improve stxvw4x implementation...
Checking PATCH 17/17: target-ppc: add stxvb16x and stxvh8x...
=== OUTPUT END ===

Test command exited with code: 1


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