From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Westerberg Subject: Re: [PATCH] pinctrl: cherryview: Do not mask all interrupts on probe Date: Wed, 14 Sep 2016 18:12:34 +0300 Message-ID: <20160914151234.GZ1811@lahna.fi.intel.com> References: <20160912090401.GB1811@lahna.fi.intel.com> <20160912130444.GB2411@ktx> <20160912131111.GG1811@lahna.fi.intel.com> <20160913093302.GL1811@lahna.fi.intel.com> <20160913125214.GO1811@lahna.fi.intel.com> <20160914082610.GV1811@lahna.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from mga11.intel.com ([192.55.52.93]:26502 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761813AbcINPOw (ORCPT ); Wed, 14 Sep 2016 11:14:52 -0400 Content-Disposition: inline In-Reply-To: Sender: linux-gpio-owner@vger.kernel.org List-Id: linux-gpio@vger.kernel.org To: Linus Walleij Cc: Marc Zyngier , Thomas Gleixner , Phidias Chiang , Anisse Astier , Heikki Krogerus , Yu C Chen , "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" On Wed, Sep 14, 2016 at 02:46:01PM +0200, Linus Walleij wrote: > > I'm going to re-read the hardware spec and see if there is anything we > > can do about this. The newer hardware (Skylake, Broxton) has a bit that > > tells the IRQ is routed directly to I/O-APIC but unfortunately Braswell > > misses that. There may be something else, though. > > So as far as we can determine: > > (A) we are running on Braswell and > (B) we are probing this driver > > we can conclude that > > (C) IRQs A,B,C are reserved by BIOS? > > That sounds doable? Yes, it's doable but that requires some hard coding in the driver :-/ I'll look into it.