From: Stephen Boyd <sboyd@codeaurora.org>
To: Jun Nie <jun.nie@linaro.org>
Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org,
shawn.guo@linaro.org, jason.liu@linaro.org
Subject: Re: [PATCH v3 1/2] clk: zx: reform pll config info to ease code extension
Date: Wed, 14 Sep 2016 13:53:31 -0700 [thread overview]
Message-ID: <20160914205331.GY7243@codeaurora.org> (raw)
In-Reply-To: <1473141762-4775-2-git-send-email-jun.nie@linaro.org>
On 09/06, Jun Nie wrote:
> Add power down bit and pll lock bit in pll config structure
> to ease new SoC support.
>
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
Applied to clk-zte and merged into clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-09-14 20:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-06 6:02 [PATCH v3 0/2] Add ZX296718 clock driver Jun Nie
2016-09-06 6:02 ` [PATCH v3 1/2] clk: zx: reform pll config info to ease code extension Jun Nie
2016-09-14 20:53 ` Stephen Boyd [this message]
2016-09-06 6:02 ` [PATCH v3 2/2] clk: zx: register ZX296718 clocks Jun Nie
2016-09-13 1:49 ` Jun Nie
2016-09-14 20:53 ` Stephen Boyd
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