From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Unlock PPS registers after GPU reset
Date: Thu, 15 Sep 2016 13:31:49 +0300 [thread overview]
Message-ID: <20160915103149.GQ4329@intel.com> (raw)
In-Reply-To: <1473847453-4771-1-git-send-email-imre.deak@intel.com>
On Wed, Sep 14, 2016 at 01:04:13PM +0300, Imre Deak wrote:
> Reapply the PPS register unlock workaround after GPU reset on platforms
> where the reset clobbers the display HW state. This at least gets rid of
> the related WARN during LVDS encoder enabling on PNV.
>
> Fixes: ed6143b8f75 ("drm/i915/lvds: Restore initial HW state during encoder enabling")
> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 48433e1..8bcffdd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3629,6 +3629,7 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
> intel_runtime_pm_disable_interrupts(dev_priv);
> intel_runtime_pm_enable_interrupts(dev_priv);
>
> + intel_pps_unlock_regs_wa(dev_priv);
> intel_modeset_init_hw(dev);
>
> spin_lock_irq(&dev_priv->irq_lock);
> --
> 2.5.0
--
Ville Syrjälä
Intel OTC
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prev parent reply other threads:[~2016-09-15 10:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-14 10:04 [PATCH] drm/i915: Unlock PPS registers after GPU reset Imre Deak
2016-09-14 10:49 ` ✓ Fi.CI.BAT: success for " Patchwork
2016-09-15 7:20 ` Patchwork
2016-09-20 12:32 ` Imre Deak
2016-09-15 10:31 ` Ville Syrjälä [this message]
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