From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bmA3M-0005gY-A3 for qemu-devel@nongnu.org; Mon, 19 Sep 2016 21:40:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bmA3H-0003dP-9s for qemu-devel@nongnu.org; Mon, 19 Sep 2016 21:40:56 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38976) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bmA3G-0003dE-W1 for qemu-devel@nongnu.org; Mon, 19 Sep 2016 21:40:51 -0400 Date: Tue, 20 Sep 2016 04:40:48 +0300 From: "Michael S. Tsirkin" Message-ID: <20160920043946-mutt-send-email-mst@kernel.org> References: <1474329904-11665-1-git-send-email-davidkiarie4@gmail.com> <1474329904-11665-3-git-send-email-davidkiarie4@gmail.com> <20160920030814-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [V18 2/4] hw/i386/trace-events: Add AMD IOMMU trace events List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Kiarie Cc: QEMU Developers , Peter Maydell , Jan Kiszka , Peter Xu On Tue, Sep 20, 2016 at 04:14:14AM +0300, David Kiarie wrote: >=20 >=20 > On Tue, Sep 20, 2016 at 3:09 AM, Michael S. Tsirkin wr= ote: >=20 > On Tue, Sep 20, 2016 at 03:05:02AM +0300, David Kiarie wrote: > > Signed-off-by: David Kiarie > > --- > >=A0 hw/i386/trace-events | 29 +++++++++++++++++++++++++++++ > >=A0 1 file changed, 29 insertions(+) > > > > diff --git a/hw/i386/trace-events b/hw/i386/trace-events > > index 5b99eba..ddeda02 100644 > > --- a/hw/i386/trace-events > > +++ b/hw/i386/trace-events > > @@ -13,3 +13,32 @@ mhp_pc_dimm_assigned_address(uint64_t addr) > "0x%"PRIx64 > > > >=A0 # hw/i386/x86-iommu.c > >=A0 x86_iommu_iec_notify(bool global, uint32_t index, uint32_t mas= k) "Notify > IEC invalidation: global=3D%d index=3D%" PRIu32 " mask=3D%" PRIu32 > > + > > +# hw/i386/amd_iommu.c > > +amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to= write > at addr 0x%"PRIx64 " +=A0 offset 0x%"PRIx32 > > +amdvi_cache_update(uint16_t domid, uint32_t bus, uint32_t slot, = uint32_t > func, uint64_t gpa, uint64_t txaddr) " update iotlb domid 0x%"PRIx1= 6" > devid: %02x:%02x.%x gpa 0x%"PRIx64 " hpa 0x%"PRIx64 > > +amdvi_completion_wait_fail(uint64_t addr) "error: fail to write = at > address 0x%"PRIx64 > > +amdvi_mmio_write(const char *reg, uint64_t addr, unsigned size, = uint64_t > val, unsigned long offset) "%s write addr 0x%"PRIx64 ", size %d, va= l > 0x%"PRIx64 ", offset 0x%"PRIx64 >=20 >=20 > unsigned long offset should be printed with %0lx not PRIx64. >=20 > There are a bunch of other bugs I fixed silenty in this file, > I don't remember where exactly pls go over and and fix > all you can find. >=20 >=20 >=20 > Separately resending this patch in the meantime just in case the rest o= f the > patchset happens not to have any more issues. > =A0 >=20 >=20 > > +amdvi_mmio_read(const char *reg, uint64_t addr, unsigned size, u= int64_t > offset) "%s read addr 0x%"PRIx64", size %d offset 0x%"PRIx64 > > +amdvi_command_error(uint64_t status) "error: Executing commands = with > command buffer disabled 0x%"PRIx64 > > +amdvi_command_read_fail(uint64_t addr, uint32_t head) "error: fa= il to > access memory at 0x%"PRIx64" + 0x%"PRIu32 > > +amdvi_command_exec(uint32_t head, uint32_t tail, uint64_t buf) "= command > buffer head at 0x%"PRIx32 " command buffer tail at 0x%"PRIx32" comm= and > buffer base at 0x%" PRIx64 > > +amdvi_unhandled_command(uint8_t type) "unhandled command %d" > > +amdvi_intr_inval(void) "Interrupt table invalidated" > > +amdvi_iotlb_inval(void) "IOTLB pages invalidated" > > +amdvi_prefetch_pages(void) "Pre-fetch of AMD-Vi pages requested" > > +amdvi_pages_inval(uint16_t domid) "AMD-Vi pages for domain 0x%"P= RIx16 " > invalidated" > > +amdvi_all_inval(void) "Invalidation of all AMD-Vi cache requeste= d " > > +amdvi_ppr_exec(void) "Execution of PPR queue requested " > > +amdvi_devtab_inval(uint16_t bus, uint16_t slot, uint16_t func) "= device > table entry for devid: %02x:%02x.%x invalidated" > > +amdvi_completion_wait(uint64_t addr, uint64_t data) "completion = wait > requested with store address 0x%"PRIx64" and store data 0x%"PRIx64 > > +amdvi_control_status(uint64_t val) "MMIO_STATUS state 0x%"PRIx64 > > +amdvi_iotlb_reset(void) "IOTLB exceed size limit - reset " > > +amdvi_completion_wait_exec(uint64_t addr, uint64_t data) "comple= tion > wait requested with store address 0x%"PRIx64" and store data 0x%"PR= Ix64 > > +amdvi_dte_get_fail(uint64_t addr, uint32_t offset) "error: faile= d to > access Device Entry devtab 0x%"PRIx64" offset 0x%"PRIx32 > > +amdvi_invalid_dte(uint64_t addr) "PTE entry at 0x%"PRIx64" is in= valid " > > +amdvi_get_pte_hwerror(uint64_t addr) "hardware error eccessing P= TE at > addr 0x%"PRIx64 > > +amdvi_mode_invalid(unsigned level, uint64_t addr)"error: transla= tion > level 0x%"PRIu8" translating addr 0x%"PRIx64 This is also wrong. Can you pls go over the traces? Also, you can check Peter Maydell's rejects of the pulls that included these patches. > > +amdvi_page_fault(uint64_t addr) "error: page fault accessing gue= st > physical address 0x%"PRIx64 > > +amdvi_iotlb_hit(uint16_t bus, uint16_t slot, uint16_t func, uint= 64_t > addr, uint64_t txaddr) "hit iotlb devid %02x:%02x.%x gpa 0x%"PRIx64= " hpa > 0x%"PRIx64 > > +amdvi_translation_result(uint16_t bus, uint16_t slot, uint16_t f= unc, > uint64_t addr, uint64_t txaddr) "devid: %02x:%02x.%x gpa 0x%"PRIx64= " hpa > 0x%"PRIx64 > > -- > > 2.1.4 >=20 >=20