From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33318) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bmJZJ-0004Zf-Ea for qemu-devel@nongnu.org; Tue, 20 Sep 2016 07:50:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bmJZC-0001q7-R1 for qemu-devel@nongnu.org; Tue, 20 Sep 2016 07:50:32 -0400 Date: Tue, 20 Sep 2016 16:39:19 +1000 From: David Gibson Message-ID: <20160920063919.GA20488@umbus> References: <1474266132-5397-1-git-send-email-nikunj@linux.vnet.ibm.com> <1474266132-5397-2-git-send-email-nikunj@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="FCPLy5NpE1Kdjj9y" Content-Disposition: inline In-Reply-To: <1474266132-5397-2-git-send-email-nikunj@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [PATCH v5 1/3] target-ppc: add TLB_NEED_LOCAL_FLUSH flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, benh@kernel.crashing.org, alex.bennee@linaro.org, qemu-devel@nongnu.org --FCPLy5NpE1Kdjj9y Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 19, 2016 at 11:52:10AM +0530, Nikunj A Dadhania wrote: > Introduces bit-flag in CPUPPCState::tlb_need_flush: >=20 > TLB_NEED_LOCAL_FLUSH (0x1) - Flush local tlb >=20 > This would indicate a pending local tlb flush (isync instructions, > interrupts, ...) >=20 > Signed-off-by: Nikunj A Dadhania Reviewed-by: David Gibson > --- > target-ppc/cpu.h | 1 + > target-ppc/helper_regs.h | 4 ++-- > target-ppc/mmu-hash64.c | 4 ++-- > target-ppc/mmu_helper.c | 6 +++--- > 4 files changed, 8 insertions(+), 7 deletions(-) >=20 > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 9617481..96d2def 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1009,6 +1009,7 @@ struct CPUPPCState { > bool tlb_dirty; /* Set to non-zero when modifying TLB = */ > bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active = */ > uint32_t tlb_need_flush; /* Delayed flush needed */ > +#define TLB_NEED_LOCAL_FLUSH 0x1 > #endif > =20 > /* Other registers */ > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h > index 3d279f1..69204a5 100644 > --- a/target-ppc/helper_regs.h > +++ b/target-ppc/helper_regs.h > @@ -157,9 +157,9 @@ static inline int hreg_store_msr(CPUPPCState *env, ta= rget_ulong value, > static inline void check_tlb_flush(CPUPPCState *env) > { > CPUState *cs =3D CPU(ppc_env_get_cpu(env)); > - if (env->tlb_need_flush) { > - env->tlb_need_flush =3D 0; > + if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { > tlb_flush(cs, 1); > + env->tlb_need_flush &=3D ~TLB_NEED_LOCAL_FLUSH; > } > } > #else > diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c > index 8118143..1f52b64 100644 > --- a/target-ppc/mmu-hash64.c > +++ b/target-ppc/mmu-hash64.c > @@ -110,7 +110,7 @@ void helper_slbia(CPUPPCState *env) > * and we still don't have a tlb_flush_mask(env, n, mas= k) > * in QEMU, we just invalidate all TLBs > */ > - env->tlb_need_flush =3D 1; > + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; > } > } > } > @@ -132,7 +132,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr) > * and we still don't have a tlb_flush_mask(env, n, mask) > * in QEMU, we just invalidate all TLBs > */ > - env->tlb_need_flush =3D 1; > + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; > } > } > =20 > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index 696bb03..d59d2f8 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1965,7 +1965,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, targe= t_ulong addr) > * we just mark the TLB to be flushed later (context synchronizi= ng > * event or sync instruction on 32-bit). > */ > - env->tlb_need_flush =3D 1; > + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; > break; > #if defined(TARGET_PPC64) > case POWERPC_MMU_64B: > @@ -1979,7 +1979,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, targe= t_ulong addr) > * and we still don't have a tlb_flush_mask(env, n, mask) i= n QEMU, > * we just invalidate all TLBs > */ > - env->tlb_need_flush =3D 1; > + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; > break; > #endif /* defined(TARGET_PPC64) */ > default: > @@ -2065,7 +2065,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong= srnum, target_ulong value) > } > } > #else > - env->tlb_need_flush =3D 1; > + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; > #endif > } > } --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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