From: Brian Norris <briannorris@chromium.org>
To: Rajat Jain <rajatja@google.com>
Cc: linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
Shawn Lin <shawn.lin@rock-chips.com>,
Jeffy Chen <jeffy.chen@rock-chips.com>,
Wenrui Li <wenrui.li@rock-chips.com>
Subject: Re: [PATCH] rockchip: Increase the Max Credit update interval.
Date: Thu, 22 Sep 2016 14:14:37 -0700 [thread overview]
Message-ID: <20160922211436.GA69457@google.com> (raw)
In-Reply-To: <1474578027-64292-1-git-send-email-rajatja@google.com>
(Nit: I think the $subject is typically 'PCI: rockchip: ...'.)
Hi Rajat,
On Thu, Sep 22, 2016 at 02:00:27PM -0700, Rajat Jain wrote:
> The register value gets lost on a Link speed/width change, and the
> ideal fix should reprogram this on that event (refer "Link Bandwidth
> Management Interrupt Enable" & "Link Autonomous Bandwidth Interrupt Enable"
> in link control reg?).
Oh, that that reminds me (sorry for not noticing this earlier): Rockchip
did add handling of those two interrupt bits. See:
} else if (reg & PCIE_CLIENT_INT_PHY) {
dev_dbg(dev, "phy link changes\n");
rockchip_pcie_clr_bw_int(rockchip);
}
Do you ever see such interrupts? In any case, it's possible we could do
the re-programming there, just to be sure, though I'm not sure we can
test it well.
Brian
next prev parent reply other threads:[~2016-09-22 21:14 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-22 21:00 [PATCH] rockchip: Increase the Max Credit update interval Rajat Jain
2016-09-22 21:14 ` Brian Norris [this message]
2016-09-22 21:56 ` Rajat Jain
2016-09-22 22:37 ` Rajat Jain
2016-09-22 22:38 ` [PATCH v2] PCI: " Rajat Jain
2016-09-23 0:42 ` Shawn Lin
2016-09-23 0:50 ` [PATCH v3] " Rajat Jain
2016-09-23 1:07 ` Shawn Lin
2016-10-04 17:17 ` Bjorn Helgaas
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