diff for duplicates of <20160928141855.GO4329@intel.com> diff --git a/a/1.txt b/N1/1.txt index deee767..3776b0c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ On Wed, Sep 28, 2016 at 02:32:19PM +0300, Ander Conselvan De Oliveira wrote: > On Mon, 2016-09-26 at 11:30 +0300, ville.syrjala@linux.intel.com wrote: -> > From: Ville Syrjälä <ville.syrjala@linux.intel.com> +> > From: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > > > DPLL_SDVO_HIGH_SPEED must be set for SDVO/HDMI/DP, but nowhere is it > > forbidden to set it for LVDS/CRT as well. So let's also set it on @@ -22,17 +22,17 @@ On Wed, Sep 28, 2016 at 02:32:19PM +0300, Ander Conselvan De Oliveira wrote: > > least for now. On ILK it never makes sense as the DPLLs can't be shared. > > > > v2: Just always enable the high speed clock to keep things simple (Daniel) -> > Beef up the commit message a bit (Daniel) +> > ����Beef up the commit message a bit (Daniel) > > > > Cc: Nick Yamane <nick.diego@gmail.com> > > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > > Cc: stable@vger.kernel.org > > Tested-by: Nick Yamane <nick.diego@gmail.com> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97204 -> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> +> > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > --- -> > drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++ -> > 1 file changed, 18 insertions(+) +> > �drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++ +> > �1 file changed, 18 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c @@ -41,15 +41,15 @@ On Wed, Sep 28, 2016 at 02:32:19PM +0300, Ander Conselvan De Oliveira wrote: > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -9512,6 +9512,24 @@ static void ironlake_compute_dpll(struct intel_crtc > > *intel_crtc, -> > if (intel_crtc_has_dp_encoder(crtc_state)) -> > dpll |= DPLL_SDVO_HIGH_SPEED; -> > +> > � if (intel_crtc_has_dp_encoder(crtc_state)) +> > � dpll |= DPLL_SDVO_HIGH_SPEED; +> > � > > + /* -> > + * The high speed IO clock is only really required for -> > + * SDVO/HDMI/DP, but we also enable it for CRT to make it -> > + * possible to share the DPLL between CRT and HDMI. Enabling -> > + * the clock needlessly does no real harm, except use up a -> > + * bit of power potentially. +> > + �* The high speed IO clock is only really required for +> > + �* SDVO/HDMI/DP, but we also enable it for CRT to make it +> > + �* possible to share the DPLL between CRT and HDMI. Enabling +> > + �* the clock needlessly does no real harm, except use up a +> > + �* bit of power potentially. > > I guess we could have a smarter way to check if two configurations are > compatible than the current memcmp(). I.e., a platform hook that takes two PLL @@ -67,23 +67,23 @@ On Wed, Sep 28, 2016 at 02:32:19PM +0300, Ander Conselvan De Oliveira wrote: Thanks. Pushed to dinq. > -> > + * -> > + * We'll limit this to IVB with 3 pipes, since it has only two -> > + * DPLLs and so DPLL sharing is the only way to get three pipes -> > + * driving PCH ports at the same time. On SNB we could do this, -> > + * and potentially avoid enabling the second DPLL, but it's not -> > + * clear if it''s a win or loss power wise. No point in doing -> > + * this on ILK at all since it has a fixed DPLL<->pipe mapping. -> > + */ +> > + �* +> > + �* We'll limit this to IVB with 3 pipes, since it has only two +> > + �* DPLLs and so DPLL sharing is the only way to get three pipes +> > + �* driving PCH ports at the same time. On SNB we could do this, +> > + �* and potentially avoid enabling the second DPLL, but it's not +> > + �* clear if it''s a win or loss power wise. No point in doing +> > + �* this on ILK at all since it has a fixed DPLL<->pipe mapping. +> > + �*/ > > + if (INTEL_INFO(dev_priv)->num_pipes == 3 && -> > + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) +> > + ����intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) > > + dpll |= DPLL_SDVO_HIGH_SPEED; > > + -> > /* compute bitmask from p1 value */ -> > dpll |= (1 << (crtc_state->dpll.p1 - 1)) << +> > � /* compute bitmask from p1 value */ +> > � dpll |= (1 << (crtc_state->dpll.p1 - 1)) << > > DPLL_FPA01_P1_POST_DIV_SHIFT; -> > /* also FPA1 */ +> > � /* also FPA1 */ -- -Ville Syrjälä +Ville Syrj�l� Intel OTC diff --git a/a/content_digest b/N1/content_digest index 285ba05..e403a7e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -12,7 +12,7 @@ "b\0" "On Wed, Sep 28, 2016 at 02:32:19PM +0300, Ander Conselvan De Oliveira wrote:\n" "> On Mon, 2016-09-26 at 11:30 +0300, ville.syrjala@linux.intel.com wrote:\n" - "> > From: Ville Syrj\303\244l\303\244 <ville.syrjala@linux.intel.com>\n" + "> > From: Ville Syrj\303\257\302\277\302\275l\303\257\302\277\302\275 <ville.syrjala@linux.intel.com>\n" "> > \n" "> > DPLL_SDVO_HIGH_SPEED must be set for SDVO/HDMI/DP, but nowhere is it\n" "> > forbidden to set it for LVDS/CRT as well. So let's also set it on\n" @@ -34,17 +34,17 @@ "> > least for now. On ILK it never makes sense as the DPLLs can't be shared.\n" "> > \n" "> > v2: Just always enable the high speed clock to keep things simple (Daniel)\n" - "> > \302\240\302\240\302\240\302\240Beef up the commit message a bit (Daniel)\n" + "> > \303\257\302\277\302\275\303\257\302\277\302\275\303\257\302\277\302\275\303\257\302\277\302\275Beef up the commit message a bit (Daniel)\n" "> > \n" "> > Cc: Nick Yamane <nick.diego@gmail.com>\n" "> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch>\n" "> > Cc: stable@vger.kernel.org\n" "> > Tested-by: Nick Yamane <nick.diego@gmail.com>\n" "> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97204\n" - "> > Signed-off-by: Ville Syrj\303\244l\303\244 <ville.syrjala@linux.intel.com>\n" + "> > Signed-off-by: Ville Syrj\303\257\302\277\302\275l\303\257\302\277\302\275 <ville.syrjala@linux.intel.com>\n" "> > ---\n" - "> > \302\240drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++\n" - "> > \302\2401 file changed, 18 insertions(+)\n" + "> > \303\257\302\277\302\275drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++\n" + "> > \303\257\302\277\302\2751 file changed, 18 insertions(+)\n" "> > \n" "> > diff --git a/drivers/gpu/drm/i915/intel_display.c\n" "> > b/drivers/gpu/drm/i915/intel_display.c\n" @@ -53,15 +53,15 @@ "> > +++ b/drivers/gpu/drm/i915/intel_display.c\n" "> > @@ -9512,6 +9512,24 @@ static void ironlake_compute_dpll(struct intel_crtc\n" "> > *intel_crtc,\n" - "> > \302\240\tif (intel_crtc_has_dp_encoder(crtc_state))\n" - "> > \302\240\t\tdpll |= DPLL_SDVO_HIGH_SPEED;\n" - "> > \302\240\n" + "> > \303\257\302\277\302\275\tif (intel_crtc_has_dp_encoder(crtc_state))\n" + "> > \303\257\302\277\302\275\t\tdpll |= DPLL_SDVO_HIGH_SPEED;\n" + "> > \303\257\302\277\302\275\n" "> > +\t/*\n" - "> > +\t\302\240* The high speed IO clock is only really required for\n" - "> > +\t\302\240* SDVO/HDMI/DP, but we also enable it for CRT to make it\n" - "> > +\t\302\240* possible to share the DPLL between CRT and HDMI. Enabling\n" - "> > +\t\302\240* the clock needlessly does no real harm, except use up a\n" - "> > +\t\302\240* bit of power potentially.\n" + "> > +\t\303\257\302\277\302\275* The high speed IO clock is only really required for\n" + "> > +\t\303\257\302\277\302\275* SDVO/HDMI/DP, but we also enable it for CRT to make it\n" + "> > +\t\303\257\302\277\302\275* possible to share the DPLL between CRT and HDMI. Enabling\n" + "> > +\t\303\257\302\277\302\275* the clock needlessly does no real harm, except use up a\n" + "> > +\t\303\257\302\277\302\275* bit of power potentially.\n" "> \n" "> I guess we could have a smarter way to check if two configurations are\n" "> compatible than the current memcmp(). I.e., a platform hook that takes two PLL\n" @@ -79,25 +79,25 @@ "Thanks. Pushed to dinq.\n" "\n" "> \n" - "> > +\t\302\240*\n" - "> > +\t\302\240* We'll limit this to IVB with 3 pipes, since it has only two\n" - "> > +\t\302\240* DPLLs and so DPLL sharing is the only way to get three pipes\n" - "> > +\t\302\240* driving PCH ports at the same time. On SNB we could do this,\n" - "> > +\t\302\240* and potentially avoid enabling the second DPLL, but it's not\n" - "> > +\t\302\240* clear if it''s a win or loss power wise. No point in doing\n" - "> > +\t\302\240* this on ILK at all since it has a fixed DPLL<->pipe mapping.\n" - "> > +\t\302\240*/\n" + "> > +\t\303\257\302\277\302\275*\n" + "> > +\t\303\257\302\277\302\275* We'll limit this to IVB with 3 pipes, since it has only two\n" + "> > +\t\303\257\302\277\302\275* DPLLs and so DPLL sharing is the only way to get three pipes\n" + "> > +\t\303\257\302\277\302\275* driving PCH ports at the same time. On SNB we could do this,\n" + "> > +\t\303\257\302\277\302\275* and potentially avoid enabling the second DPLL, but it's not\n" + "> > +\t\303\257\302\277\302\275* clear if it''s a win or loss power wise. No point in doing\n" + "> > +\t\303\257\302\277\302\275* this on ILK at all since it has a fixed DPLL<->pipe mapping.\n" + "> > +\t\303\257\302\277\302\275*/\n" "> > +\tif (INTEL_INFO(dev_priv)->num_pipes == 3 &&\n" - "> > +\t\302\240\302\240\302\240\302\240intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))\n" + "> > +\t\303\257\302\277\302\275\303\257\302\277\302\275\303\257\302\277\302\275\303\257\302\277\302\275intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))\n" "> > +\t\tdpll |= DPLL_SDVO_HIGH_SPEED;\n" "> > +\n" - "> > \302\240\t/* compute bitmask from p1 value */\n" - "> > \302\240\tdpll |= (1 << (crtc_state->dpll.p1 - 1)) <<\n" + "> > \303\257\302\277\302\275\t/* compute bitmask from p1 value */\n" + "> > \303\257\302\277\302\275\tdpll |= (1 << (crtc_state->dpll.p1 - 1)) <<\n" "> > DPLL_FPA01_P1_POST_DIV_SHIFT;\n" - "> > \302\240\t/* also FPA1 */\n" + "> > \303\257\302\277\302\275\t/* also FPA1 */\n" "\n" "-- \n" - "Ville Syrj\303\244l\303\244\n" + "Ville Syrj\303\257\302\277\302\275l\303\257\302\277\302\275\n" Intel OTC -b0d36b69db548963d4056f75df971602a4cee8920e2fe216c9128437357c8b56 +56be06cd467a74a9f4c17604eb587af7e17ea38b5c80380869e628ae974fe0fd
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