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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id g7sm2759732ljg.44.2016.10.06.09.55.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Oct 2016 09:55:10 -0700 (PDT) Date: Thu, 6 Oct 2016 18:55:09 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20161006165509.GA28109@toto> References: <1475760067-25756-1-git-send-email-peter.maydell@linaro.org> <1475760067-25756-2-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1475760067-25756-2-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c07::244 Subject: Re: [Qemu-arm] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: kMWtnf/Hn6sD On Thu, Oct 06, 2016 at 02:21:05PM +0100, Peter Maydell wrote: > MDCCINT_EL1 is part of the DCC debugger communication > channel between the CPU and an attached external debugger. > QEMU doesn't implement this, but since Linux may try > to access this register we need to provide at least > a dummy implementation. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 25f612d..23792ab 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, > .access = PL1_RW, .accessfn = access_tda, > .type = ARM_CP_NOP }, > + /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications > + * Channel but Linux may try to access this register. The 32-bit > + * alias is DBGDCCINT. > + */ > + { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, > + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, > + .access = PL1_RW, .accessfn = access_tda, > + .type = ARM_CP_NOP }, > REGINFO_SENTINEL > }; > > -- > 2.7.4 > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40680) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bsBx2-0004fN-OZ for qemu-devel@nongnu.org; Thu, 06 Oct 2016 12:55:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bsBx1-0007wj-GG for qemu-devel@nongnu.org; Thu, 06 Oct 2016 12:55:20 -0400 Date: Thu, 6 Oct 2016 18:55:09 +0200 From: "Edgar E. Iglesias" Message-ID: <20161006165509.GA28109@toto> References: <1475760067-25756-1-git-send-email-peter.maydell@linaro.org> <1475760067-25756-2-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1475760067-25756-2-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 1/3] target-arm: Implement dummy MDCCINT_EL1 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org On Thu, Oct 06, 2016 at 02:21:05PM +0100, Peter Maydell wrote: > MDCCINT_EL1 is part of the DCC debugger communication > channel between the CPU and an attached external debugger. > QEMU doesn't implement this, but since Linux may try > to access this register we need to provide at least > a dummy implementation. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/helper.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 25f612d..23792ab 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { > .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0, > .access = PL1_RW, .accessfn = access_tda, > .type = ARM_CP_NOP }, > + /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications > + * Channel but Linux may try to access this register. The 32-bit > + * alias is DBGDCCINT. > + */ > + { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH, > + .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0, > + .access = PL1_RW, .accessfn = access_tda, > + .type = ARM_CP_NOP }, > REGINFO_SENTINEL > }; > > -- > 2.7.4 >