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[81.231.233.234]) by smtp.gmail.com with ESMTPSA id 23sm2848480ljf.9.2016.10.06.09.59.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Oct 2016 09:59:22 -0700 (PDT) Date: Thu, 6 Oct 2016 18:59:21 +0200 From: "Edgar E. Iglesias" To: Peter Maydell Message-ID: <20161006165921.GD28109@toto> References: <1475760067-25756-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1475760067-25756-1-git-send-email-peter.maydell@linaro.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c07::244 Subject: Re: [Qemu-devel] [PATCH 0/3] preliminaries for GICv3 virt support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org Errors-To: qemu-devel-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-devel" X-TUID: eaff/kQkorZR On Thu, Oct 06, 2016 at 02:21:04PM +0100, Peter Maydell wrote: > This set of three straightforward patches is a preliminary > for adding virtualization support to the GICv3 emulation: > * add a (nop implementation of) MDCCINT_EL1, since KVM > will read/write it on worldswitch > * fix some bugs in the GICv3 trace events > * add trace events for the generic timers > (which I have been using for debugging) > > I actually have almost all of the GICv3 virt code written, > but it currently has bugs which mean that a guest kernel > under KVM won't boot. Debugging in progress... That is very cool, we could soon enable EL2 :-) What kind of issues are you seeing? FWIW with our out of tree GICv2 virt models we've got issues with SMP Xen were things go nuts some times with virtual timer interrupts. Some times they take for ever to hit, like if we loose events. Last time I looked at it, I noticed that our GICv2 virt implementation of the APR regs and EOIR stuff seems totally bogus (my bad). Cheers, Edgar > > thanks > -- PMM > > Peter Maydell (3): > target-arm: Implement dummy MDCCINT_EL1 > target-arm: Add trace events for the generic timers > hw/intc/arm_gicv3: Fix ICC register tracepoints > > Makefile.objs | 1 + > hw/intc/arm_gicv3_cpuif.c | 23 +++++++++++++++-------- > hw/intc/trace-events | 14 +++++++------- > target-arm/helper.c | 28 ++++++++++++++++++++++++---- > 4 files changed, 47 insertions(+), 19 deletions(-) > > -- > 2.7.4 >