From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44693) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bsMpo-0005ZL-9e for qemu-devel@nongnu.org; Fri, 07 Oct 2016 00:32:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bsMpm-0007k0-MO for qemu-devel@nongnu.org; Fri, 07 Oct 2016 00:32:36 -0400 Date: Fri, 7 Oct 2016 15:32:21 +1100 From: David Gibson Message-ID: <20161007043221.GS18490@umbus.fritz.box> References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-4-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bAwSoJxbKYwy34Oe" Content-Disposition: inline In-Reply-To: <1475479496-16158-4-git-send-email-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH v4 03/20] ppc/pnv: add a core mask to PnvChip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org --bAwSoJxbKYwy34Oe Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 03, 2016 at 09:24:39AM +0200, C=E9dric Le Goater wrote: > This will be used to build real HW ids for the cores and enforce some > limits on the available cores per chip. Is there actually a practical reason to allow the user (or machine type) to override the default core mask? >=20 > Signed-off-by: C=E9dric Le Goater Apart from the above and one comment below, Reviewed-by: David Gibson > --- >=20 > Changes since v3 : >=20 > - reworked pnv_chip_core_sanitize() to return errors and to check the > maximum of cores against the instance cores_mask > =20 > Changes since v2 : >=20 > - added POWER9 support > - removed cores_max=20 > - introduces a pnv_chip_core_sanitize() helper to check the core > ids_mask and the maximum number of cores >=20 > hw/ppc/pnv.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++= +++++- > include/hw/ppc/pnv.h | 4 +++ > 2 files changed, 81 insertions(+), 1 deletion(-) >=20 > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 08f72dbdca97..fc930be94f53 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -227,11 +227,44 @@ static void ppc_powernv_init(MachineState *machine) > snprintf(chip_name, sizeof(chip_name), "chip[%d]", CHIP_HWID(i)); > object_property_add_child(OBJECT(pnv), chip_name, chip, &error_f= atal); > object_property_set_int(chip, CHIP_HWID(i), "chip-id", &error_fa= tal); > + object_property_set_int(chip, smp_cores, "nr-cores", &error_fata= l); > + /* > + * We could customize cores_mask for the chip here. May be > + * using a powernv machine property, like 'num-chips'. Let the > + * chip choose the default for now. I don't think you need any special mechanism for this. If you just remove this explicit assignment the chip default will apply, but the user can alter it using -global. > + */ > + object_property_set_int(chip, 0x0, "cores-mask", &error_fatal); > object_property_set_bool(chip, true, "realized", &error_fatal); > } > g_free(chip_typename); > } > =20 > +/* Allowed core identifiers on a POWER8 Processor Chip : > + * > + * > + * EX1 - Venice only > + * EX2 - Venice only > + * EX3 - Venice only > + * EX4 > + * EX5 > + * EX6 > + * > + * EX9 - Venice only > + * EX10 - Venice only > + * EX11 - Venice only > + * EX12 > + * EX13 > + * EX14 > + * > + */ > +#define POWER8E_CORE_MASK (0x7070ull) > +#define POWER8_CORE_MASK (0x7e7eull) > + > +/* > + * POWER9 has 24 cores, ids starting at 0x20 > + */ > +#define POWER9_CORE_MASK (0xffffff00000000ull) > + > static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > @@ -240,6 +273,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) > k->cpu_model =3D "POWER8E"; > k->chip_type =3D PNV_CHIP_POWER8E; > k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ > + k->cores_mask =3D POWER8E_CORE_MASK; > dc->desc =3D "PowerNV Chip POWER8E"; > } > =20 > @@ -258,6 +292,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) > k->cpu_model =3D "POWER8"; > k->chip_type =3D PNV_CHIP_POWER8; > k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ > + k->cores_mask =3D POWER8_CORE_MASK; > dc->desc =3D "PowerNV Chip POWER8"; > } > =20 > @@ -276,6 +311,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) > k->cpu_model =3D "POWER8NVL"; > k->chip_type =3D PNV_CHIP_POWER8NVL; > k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ > + k->cores_mask =3D POWER8_CORE_MASK; > dc->desc =3D "PowerNV Chip POWER8NVL"; > } > =20 > @@ -294,6 +330,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) > k->cpu_model =3D "POWER9"; > k->chip_type =3D PNV_CHIP_POWER9; > k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ > + k->cores_mask =3D POWER9_CORE_MASK; > dc->desc =3D "PowerNV Chip POWER9"; > } > =20 > @@ -304,13 +341,52 @@ static const TypeInfo pnv_chip_power9_info =3D { > .class_init =3D pnv_chip_power9_class_init, > }; > =20 > +static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) > +{ > + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); > + int cores_max; > + > + /* > + * No custom mask for this chip, let's use the default one from * > + * the chip class > + */ > + if (!chip->cores_mask) { > + chip->cores_mask =3D pcc->cores_mask; > + } > + > + /* filter alien core ids ! some are reserved */ > + if ((chip->cores_mask & pcc->cores_mask) !=3D chip->cores_mask) { > + error_setg(errp, "warning: invalid core mask for chip !"); > + return; > + } > + chip->cores_mask &=3D pcc->cores_mask; > + > + /* now that we have a sane layout, let check the number of cores */ > + cores_max =3D hweight_long(chip->cores_mask); > + if (chip->nr_cores > cores_max) { > + error_setg(errp, "warning: too many cores for chip ! Limit is %d= ", > + cores_max); > + return; > + } > +} > + > static void pnv_chip_realize(DeviceState *dev, Error **errp) > { > - /* left purposely empty */ > + PnvChip *chip =3D PNV_CHIP(dev); > + Error *error =3D NULL; > + > + /* Early checks on the core settings */ > + pnv_chip_core_sanitize(chip, &error); > + if (error) { > + error_propagate(errp, error); > + return; > + } > } > =20 > static Property pnv_chip_properties[] =3D { > DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), > + DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), > + DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index da543ed81636..2c225c928974 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -42,6 +42,9 @@ typedef struct PnvChip { > =20 > /*< public >*/ > uint32_t chip_id; > + > + uint32_t nr_cores; > + uint64_t cores_mask; > } PnvChip; > =20 > typedef struct PnvChipClass { > @@ -52,6 +55,7 @@ typedef struct PnvChipClass { > const char *cpu_model; > PnvChipType chip_type; > uint64_t chip_cfam_id; > + uint64_t cores_mask; > } PnvChipClass; > =20 > #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E" --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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