From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH] arm64: KVM: Take S1 walks into account when determining S2 write faults Date: Mon, 17 Oct 2016 11:20:22 +0100 Message-ID: <20161017102022.GB1442@arm.com> References: <1475149021-13288-1-git-send-email-will.deacon@arm.com> <20160929191432.GA7996@cbox> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id DCC0040FA2 for ; Mon, 17 Oct 2016 06:10:09 -0400 (EDT) Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kJ1VcFdiyQMF for ; Mon, 17 Oct 2016 06:10:04 -0400 (EDT) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by mm01.cs.columbia.edu (Postfix) with ESMTP id C615B40C9D for ; Mon, 17 Oct 2016 06:10:04 -0400 (EDT) Content-Disposition: inline In-Reply-To: <20160929191432.GA7996@cbox> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu To: Christoffer Dall Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org List-Id: kvmarm@lists.cs.columbia.edu On Thu, Sep 29, 2016 at 09:14:32PM +0200, Christoffer Dall wrote: > On Thu, Sep 29, 2016 at 12:37:01PM +0100, Will Deacon wrote: > > The WnR bit in the HSR/ESR_EL2 indicates whether a data abort was > > generated by a read or a write instruction. For stage 2 data aborts > > generated by a stage 1 translation table walk (i.e. the actual page > > table access faults at EL2), the WnR bit therefore reports whether the > > instruction generating the walk was a load or a store, *not* whether the > > page table walker was reading or writing the entry. > > > > For page tables marked as read-only at stage 2 (e.g. due to KSM merging > > them with the tables from another guest), this could result in livelock, > > where a page table walk generated by a load instruction attempts to > > set the access flag in the stage 1 descriptor, but fails to trigger > > CoW in the host since only a read fault is reported. > > > > This patch modifies the arm64 kvm_vcpu_dabt_iswrite function to > > take into account stage 2 faults in stage 1 walks. Since DBM cannot be > > disabled at EL2 for CPUs that implement it, we assume that these faults > > are always causes by writes, avoiding the livelock situation at the > > expense of occasional, spurious CoWs. > > > > We could, in theory, do a bit better by checking the guest TCR > > configuration and inspecting the page table to see why the PTE faulted. > > However, I doubt this is measurable in practice, and the threat of > > livelock is real. > > > > Cc: Marc Zyngier > > Cc: Christoffer Dall > > Cc: Julien Grall > > Signed-off-by: Will Deacon > > Reviewed-by: Christoffer Dall > > Applied, This doesn't seem to be in 4.9-rc1. Could you please dig it up? Ta, Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Mon, 17 Oct 2016 11:20:22 +0100 Subject: [PATCH] arm64: KVM: Take S1 walks into account when determining S2 write faults In-Reply-To: <20160929191432.GA7996@cbox> References: <1475149021-13288-1-git-send-email-will.deacon@arm.com> <20160929191432.GA7996@cbox> Message-ID: <20161017102022.GB1442@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Sep 29, 2016 at 09:14:32PM +0200, Christoffer Dall wrote: > On Thu, Sep 29, 2016 at 12:37:01PM +0100, Will Deacon wrote: > > The WnR bit in the HSR/ESR_EL2 indicates whether a data abort was > > generated by a read or a write instruction. For stage 2 data aborts > > generated by a stage 1 translation table walk (i.e. the actual page > > table access faults at EL2), the WnR bit therefore reports whether the > > instruction generating the walk was a load or a store, *not* whether the > > page table walker was reading or writing the entry. > > > > For page tables marked as read-only at stage 2 (e.g. due to KSM merging > > them with the tables from another guest), this could result in livelock, > > where a page table walk generated by a load instruction attempts to > > set the access flag in the stage 1 descriptor, but fails to trigger > > CoW in the host since only a read fault is reported. > > > > This patch modifies the arm64 kvm_vcpu_dabt_iswrite function to > > take into account stage 2 faults in stage 1 walks. Since DBM cannot be > > disabled at EL2 for CPUs that implement it, we assume that these faults > > are always causes by writes, avoiding the livelock situation at the > > expense of occasional, spurious CoWs. > > > > We could, in theory, do a bit better by checking the guest TCR > > configuration and inspecting the page table to see why the PTE faulted. > > However, I doubt this is measurable in practice, and the threat of > > livelock is real. > > > > Cc: Marc Zyngier > > Cc: Christoffer Dall > > Cc: Julien Grall > > Signed-off-by: Will Deacon > > Reviewed-by: Christoffer Dall > > Applied, This doesn't seem to be in 4.9-rc1. Could you please dig it up? Ta, Will