diff for duplicates of <20161017160941.4205-2-atull@opensource.altera.com> diff --git a/a/1.txt b/N1/1.txt index 7ed2831..56ed267 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -13,7 +13,7 @@ v11: No change in this patch for v11 of the patch set v12: Moved out of staging. Changed to use FPGA bridges framework instead of resets for bridges. -v13: bridge at 0xff20000 -> bridge at ff200000, etc +v13: bridge@0xff20000 -> bridge@ff200000, etc Leave out directly talking about overlays Remove regs and clocks directly under simple-fpga-bus in example Use common "firmware-name" binding instead of "fpga-firmware" @@ -265,14 +265,14 @@ index 0000000..3b32ba1 +Example: +Base tree contains: + -+ fpga_mgr: fpga-mgr at ff706000 { ++ fpga_mgr: fpga-mgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000 + 0xffb90000 0x20>; + interrupts = <0 175 4>; + }; + -+ fpga_bridge0: fpga-bridge at ff400000 { ++ fpga_bridge0: fpga-bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; @@ -288,7 +288,7 @@ index 0000000..3b32ba1 + }; + }; + -+ fpga_bridge1: fpga-bridge at ff500000 { ++ fpga_bridge1: fpga-bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; @@ -299,7 +299,7 @@ index 0000000..3b32ba1 + +/dts-v1/ /plugin/; +/ { -+ fragment at 0 { ++ fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; @@ -312,7 +312,7 @@ index 0000000..3b32ba1 + ranges = <0x20000 0xff200000 0x100000>, + <0x0 0xc0000000 0x20000000>; + -+ gpio at 10040 { ++ gpio@10040 { + compatible = "altr,pio-1.0"; + reg = <0x10040 0x20>; + altr,gpio-bank-width = <4>; @@ -404,7 +404,7 @@ index 0000000..3b32ba1 +========================================================= + +Live Device Tree contains: -+ fpga_mgr0: fpga-mgr at f8007000 { ++ fpga_mgr0: fpga-mgr@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; + interrupt-parent = <&intc>; @@ -425,7 +425,7 @@ index 0000000..3b32ba1 +DT Overlay contains: +/dts-v1/ /plugin/; +/ { -+fragment at 0 { ++fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; @@ -435,7 +435,7 @@ index 0000000..3b32ba1 + + firmware-name = "zynq-gpio.bin"; + -+ gpio1: gpio at 40000000 { ++ gpio1: gpio@40000000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0x40000000 0x10000>; + gpio-controller; @@ -456,7 +456,7 @@ index 0000000..3b32ba1 +DT Overlay contains: +/dts-v1/ /plugin/; +/ { -+ fragment at 0 { ++ fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; @@ -466,7 +466,7 @@ index 0000000..3b32ba1 + + firmware-name = "base.rbf"; + -+ fpga-bridge at 4400 { ++ fpga-bridge@4400 { + compatible = "altr,freeze-bridge"; + reg = <0x4400 0x10>; + @@ -478,7 +478,7 @@ index 0000000..3b32ba1 + }; + }; + -+ fpga-bridge at 4420 { ++ fpga-bridge@4420 { + compatible = "altr,freeze-bridge"; + reg = <0x4420 0x10>; + @@ -505,7 +505,7 @@ index 0000000..3b32ba1 + +/dts-v1/ /plugin/; +/ { -+ fragment at 0 { ++ fragment@0 { + target = <&fpga_region1>; + #address-cells = <1>; + #size-cells = <1>; @@ -516,7 +516,7 @@ index 0000000..3b32ba1 + firmware-name = "soc_image2.rbf"; + partial-fpga-config; + -+ gpio at 10040 { ++ gpio@10040 { + compatible = "altr,pio-1.0"; + reg = <0x10040 0x20>; + clocks = <0x2>; diff --git a/a/content_digest b/N1/content_digest index 6aa0002..baa499a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,25 @@ "ref\020161017160941.4205-1-atull@opensource.altera.com\0" - "From\0atull@opensource.altera.com (Alan Tull)\0" + "From\0Alan Tull <atull@opensource.altera.com>\0" "Subject\0[PATCH v20 01/10] fpga: add bindings document for fpga region\0" "Date\0Mon, 17 Oct 2016 11:09:32 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robh+dt@kernel.org>\0" + "Cc\0Mark Rutland <mark.rutland@arm.com>" + Moritz Fischer <moritz.fischer@ettus.com> + delicious.quinoa@gmail.com + Ian Campbell <ijc+devicetree@hellion.org.uk> + Alan Tull <atull@opensource.altera.com> + Greg Kroah-Hartman <gregkh@linuxfoundation.org> + Jonathan Corbet <corbet@lwn.net> + linux-doc@vger.kernel.org + Michal Simek <michal.simek@xilinx.com> + linux-kernel@vger.kernel.org + Cyril Chemparathy <cyril.chemparathy@xilinx.com> + devicetree@vger.kernel.org + Jon Masters <jcm@redhat.com> + Matthew Gerlach <mgerlach@opensource.altera.com> + Frank Rowand <frowand.list@gmail.com> + Dinh Nguyen <dinguyen@opensource.altera.com> + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "New bindings document for FPGA Region to support programming\n" @@ -20,7 +37,7 @@ "v12: Moved out of staging.\n" " Changed to use FPGA bridges framework instead of resets\n" " for bridges.\n" - "v13: bridge at 0xff20000 -> bridge at ff200000, etc\n" + "v13: bridge@0xff20000 -> bridge@ff200000, etc\n" " Leave out directly talking about overlays\n" " Remove regs and clocks directly under simple-fpga-bus in example\n" " Use common \"firmware-name\" binding instead of \"fpga-firmware\"\n" @@ -272,14 +289,14 @@ "+Example:\n" "+Base tree contains:\n" "+\n" - "+\tfpga_mgr: fpga-mgr at ff706000 {\n" + "+\tfpga_mgr: fpga-mgr@ff706000 {\n" "+\t\tcompatible = \"altr,socfpga-fpga-mgr\";\n" "+\t\treg = <0xff706000 0x1000\n" "+\t\t 0xffb90000 0x20>;\n" "+\t\tinterrupts = <0 175 4>;\n" "+\t};\n" "+\n" - "+\tfpga_bridge0: fpga-bridge at ff400000 {\n" + "+\tfpga_bridge0: fpga-bridge@ff400000 {\n" "+\t\tcompatible = \"altr,socfpga-lwhps2fpga-bridge\";\n" "+\t\treg = <0xff400000 0x100000>;\n" "+\t\tresets = <&rst LWHPS2FPGA_RESET>;\n" @@ -295,7 +312,7 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tfpga_bridge1: fpga-bridge at ff500000 {\n" + "+\tfpga_bridge1: fpga-bridge@ff500000 {\n" "+\t\tcompatible = \"altr,socfpga-hps2fpga-bridge\";\n" "+\t\treg = <0xff500000 0x10000>;\n" "+\t\tresets = <&rst HPS2FPGA_RESET>;\n" @@ -306,7 +323,7 @@ "+\n" "+/dts-v1/ /plugin/;\n" "+/ {\n" - "+\tfragment at 0 {\n" + "+\tfragment@0 {\n" "+\t\ttarget = <&fpga_region0>;\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" @@ -319,7 +336,7 @@ "+\t\t\tranges = <0x20000 0xff200000 0x100000>,\n" "+\t\t\t\t <0x0 0xc0000000 0x20000000>;\n" "+\n" - "+\t\t\tgpio at 10040 {\n" + "+\t\t\tgpio@10040 {\n" "+\t\t\t\tcompatible = \"altr,pio-1.0\";\n" "+\t\t\t\treg = <0x10040 0x20>;\n" "+\t\t\t\taltr,gpio-bank-width = <4>;\n" @@ -411,7 +428,7 @@ "+=========================================================\n" "+\n" "+Live Device Tree contains:\n" - "+\tfpga_mgr0: fpga-mgr at f8007000 {\n" + "+\tfpga_mgr0: fpga-mgr@f8007000 {\n" "+\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n" "+\t\treg = <0xf8007000 0x100>;\n" "+\t\tinterrupt-parent = <&intc>;\n" @@ -432,7 +449,7 @@ "+DT Overlay contains:\n" "+/dts-v1/ /plugin/;\n" "+/ {\n" - "+fragment at 0 {\n" + "+fragment@0 {\n" "+\ttarget = <&fpga_region0>;\n" "+\t#address-cells = <1>;\n" "+\t#size-cells = <1>;\n" @@ -442,7 +459,7 @@ "+\n" "+\t\tfirmware-name = \"zynq-gpio.bin\";\n" "+\n" - "+\t\tgpio1: gpio at 40000000 {\n" + "+\t\tgpio1: gpio@40000000 {\n" "+\t\t\tcompatible = \"xlnx,xps-gpio-1.00.a\";\n" "+\t\t\treg = <0x40000000 0x10000>;\n" "+\t\t\tgpio-controller;\n" @@ -463,7 +480,7 @@ "+DT Overlay contains:\n" "+/dts-v1/ /plugin/;\n" "+/ {\n" - "+\tfragment at 0 {\n" + "+\tfragment@0 {\n" "+\t\ttarget = <&fpga_region0>;\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" @@ -473,7 +490,7 @@ "+\n" "+\t\t\tfirmware-name = \"base.rbf\";\n" "+\n" - "+\t\t\tfpga-bridge at 4400 {\n" + "+\t\t\tfpga-bridge@4400 {\n" "+\t\t\t\tcompatible = \"altr,freeze-bridge\";\n" "+\t\t\t\treg = <0x4400 0x10>;\n" "+\n" @@ -485,7 +502,7 @@ "+\t\t\t\t};\n" "+\t\t\t};\n" "+\n" - "+\t\t\tfpga-bridge at 4420 {\n" + "+\t\t\tfpga-bridge@4420 {\n" "+\t\t\t\tcompatible = \"altr,freeze-bridge\";\n" "+\t\t\t\treg = <0x4420 0x10>;\n" "+\n" @@ -512,7 +529,7 @@ "+\n" "+/dts-v1/ /plugin/;\n" "+/ {\n" - "+\tfragment at 0 {\n" + "+\tfragment@0 {\n" "+\t\ttarget = <&fpga_region1>;\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" @@ -523,7 +540,7 @@ "+\t\t\tfirmware-name = \"soc_image2.rbf\";\n" "+\t\t\tpartial-fpga-config;\n" "+\n" - "+\t\t\tgpio at 10040 {\n" + "+\t\t\tgpio@10040 {\n" "+\t\t\t\tcompatible = \"altr,pio-1.0\";\n" "+\t\t\t\treg = <0x10040 0x20>;\n" "+\t\t\t\tclocks = <0x2>;\n" @@ -557,4 +574,4 @@ "-- \n" 2.10.1 -21219695d9941bbd5229859b5fcf08b3e743cc6470731b6cdf0b88350efb8588 +5308abe942f3bb5140d083d3c7b36f5a63a9b0c3733b72ec3ef3ddba33c5be4f
diff --git a/a/1.txt b/N2/1.txt index 7ed2831..56ed267 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -13,7 +13,7 @@ v11: No change in this patch for v11 of the patch set v12: Moved out of staging. Changed to use FPGA bridges framework instead of resets for bridges. -v13: bridge at 0xff20000 -> bridge at ff200000, etc +v13: bridge@0xff20000 -> bridge@ff200000, etc Leave out directly talking about overlays Remove regs and clocks directly under simple-fpga-bus in example Use common "firmware-name" binding instead of "fpga-firmware" @@ -265,14 +265,14 @@ index 0000000..3b32ba1 +Example: +Base tree contains: + -+ fpga_mgr: fpga-mgr at ff706000 { ++ fpga_mgr: fpga-mgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000 + 0xffb90000 0x20>; + interrupts = <0 175 4>; + }; + -+ fpga_bridge0: fpga-bridge at ff400000 { ++ fpga_bridge0: fpga-bridge@ff400000 { + compatible = "altr,socfpga-lwhps2fpga-bridge"; + reg = <0xff400000 0x100000>; + resets = <&rst LWHPS2FPGA_RESET>; @@ -288,7 +288,7 @@ index 0000000..3b32ba1 + }; + }; + -+ fpga_bridge1: fpga-bridge at ff500000 { ++ fpga_bridge1: fpga-bridge@ff500000 { + compatible = "altr,socfpga-hps2fpga-bridge"; + reg = <0xff500000 0x10000>; + resets = <&rst HPS2FPGA_RESET>; @@ -299,7 +299,7 @@ index 0000000..3b32ba1 + +/dts-v1/ /plugin/; +/ { -+ fragment at 0 { ++ fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; @@ -312,7 +312,7 @@ index 0000000..3b32ba1 + ranges = <0x20000 0xff200000 0x100000>, + <0x0 0xc0000000 0x20000000>; + -+ gpio at 10040 { ++ gpio@10040 { + compatible = "altr,pio-1.0"; + reg = <0x10040 0x20>; + altr,gpio-bank-width = <4>; @@ -404,7 +404,7 @@ index 0000000..3b32ba1 +========================================================= + +Live Device Tree contains: -+ fpga_mgr0: fpga-mgr at f8007000 { ++ fpga_mgr0: fpga-mgr@f8007000 { + compatible = "xlnx,zynq-devcfg-1.0"; + reg = <0xf8007000 0x100>; + interrupt-parent = <&intc>; @@ -425,7 +425,7 @@ index 0000000..3b32ba1 +DT Overlay contains: +/dts-v1/ /plugin/; +/ { -+fragment at 0 { ++fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; @@ -435,7 +435,7 @@ index 0000000..3b32ba1 + + firmware-name = "zynq-gpio.bin"; + -+ gpio1: gpio at 40000000 { ++ gpio1: gpio@40000000 { + compatible = "xlnx,xps-gpio-1.00.a"; + reg = <0x40000000 0x10000>; + gpio-controller; @@ -456,7 +456,7 @@ index 0000000..3b32ba1 +DT Overlay contains: +/dts-v1/ /plugin/; +/ { -+ fragment at 0 { ++ fragment@0 { + target = <&fpga_region0>; + #address-cells = <1>; + #size-cells = <1>; @@ -466,7 +466,7 @@ index 0000000..3b32ba1 + + firmware-name = "base.rbf"; + -+ fpga-bridge at 4400 { ++ fpga-bridge@4400 { + compatible = "altr,freeze-bridge"; + reg = <0x4400 0x10>; + @@ -478,7 +478,7 @@ index 0000000..3b32ba1 + }; + }; + -+ fpga-bridge at 4420 { ++ fpga-bridge@4420 { + compatible = "altr,freeze-bridge"; + reg = <0x4420 0x10>; + @@ -505,7 +505,7 @@ index 0000000..3b32ba1 + +/dts-v1/ /plugin/; +/ { -+ fragment at 0 { ++ fragment@0 { + target = <&fpga_region1>; + #address-cells = <1>; + #size-cells = <1>; @@ -516,7 +516,7 @@ index 0000000..3b32ba1 + firmware-name = "soc_image2.rbf"; + partial-fpga-config; + -+ gpio at 10040 { ++ gpio@10040 { + compatible = "altr,pio-1.0"; + reg = <0x10040 0x20>; + clocks = <0x2>; diff --git a/a/content_digest b/N2/content_digest index 6aa0002..54db933 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,8 +1,25 @@ "ref\020161017160941.4205-1-atull@opensource.altera.com\0" - "From\0atull@opensource.altera.com (Alan Tull)\0" + "From\0Alan Tull <atull@opensource.altera.com>\0" "Subject\0[PATCH v20 01/10] fpga: add bindings document for fpga region\0" "Date\0Mon, 17 Oct 2016 11:09:32 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robh+dt@kernel.org>\0" + "Cc\0Frank Rowand <frowand.list@gmail.com>" + Mark Rutland <mark.rutland@arm.com> + Greg Kroah-Hartman <gregkh@linuxfoundation.org> + Moritz Fischer <moritz.fischer@ettus.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Jon Masters <jcm@redhat.com> + Michal Simek <michal.simek@xilinx.com> + Jonathan Corbet <corbet@lwn.net> + Cyril Chemparathy <cyril.chemparathy@xilinx.com> + Matthew Gerlach <mgerlach@opensource.altera.com> + Dinh Nguyen <dinguyen@opensource.altera.com> + <devicetree@vger.kernel.org> + <linux-doc@vger.kernel.org> + <linux-arm-kernel@lists.infradead.org> + <linux-kernel@vger.kernel.org> + <delicious.quinoa@gmail.com> + " Alan Tull <atull@opensource.altera.com>\0" "\00:1\0" "b\0" "New bindings document for FPGA Region to support programming\n" @@ -20,7 +37,7 @@ "v12: Moved out of staging.\n" " Changed to use FPGA bridges framework instead of resets\n" " for bridges.\n" - "v13: bridge at 0xff20000 -> bridge at ff200000, etc\n" + "v13: bridge@0xff20000 -> bridge@ff200000, etc\n" " Leave out directly talking about overlays\n" " Remove regs and clocks directly under simple-fpga-bus in example\n" " Use common \"firmware-name\" binding instead of \"fpga-firmware\"\n" @@ -272,14 +289,14 @@ "+Example:\n" "+Base tree contains:\n" "+\n" - "+\tfpga_mgr: fpga-mgr at ff706000 {\n" + "+\tfpga_mgr: fpga-mgr@ff706000 {\n" "+\t\tcompatible = \"altr,socfpga-fpga-mgr\";\n" "+\t\treg = <0xff706000 0x1000\n" "+\t\t 0xffb90000 0x20>;\n" "+\t\tinterrupts = <0 175 4>;\n" "+\t};\n" "+\n" - "+\tfpga_bridge0: fpga-bridge at ff400000 {\n" + "+\tfpga_bridge0: fpga-bridge@ff400000 {\n" "+\t\tcompatible = \"altr,socfpga-lwhps2fpga-bridge\";\n" "+\t\treg = <0xff400000 0x100000>;\n" "+\t\tresets = <&rst LWHPS2FPGA_RESET>;\n" @@ -295,7 +312,7 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tfpga_bridge1: fpga-bridge at ff500000 {\n" + "+\tfpga_bridge1: fpga-bridge@ff500000 {\n" "+\t\tcompatible = \"altr,socfpga-hps2fpga-bridge\";\n" "+\t\treg = <0xff500000 0x10000>;\n" "+\t\tresets = <&rst HPS2FPGA_RESET>;\n" @@ -306,7 +323,7 @@ "+\n" "+/dts-v1/ /plugin/;\n" "+/ {\n" - "+\tfragment at 0 {\n" + "+\tfragment@0 {\n" "+\t\ttarget = <&fpga_region0>;\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" @@ -319,7 +336,7 @@ "+\t\t\tranges = <0x20000 0xff200000 0x100000>,\n" "+\t\t\t\t <0x0 0xc0000000 0x20000000>;\n" "+\n" - "+\t\t\tgpio at 10040 {\n" + "+\t\t\tgpio@10040 {\n" "+\t\t\t\tcompatible = \"altr,pio-1.0\";\n" "+\t\t\t\treg = <0x10040 0x20>;\n" "+\t\t\t\taltr,gpio-bank-width = <4>;\n" @@ -411,7 +428,7 @@ "+=========================================================\n" "+\n" "+Live Device Tree contains:\n" - "+\tfpga_mgr0: fpga-mgr at f8007000 {\n" + "+\tfpga_mgr0: fpga-mgr@f8007000 {\n" "+\t\tcompatible = \"xlnx,zynq-devcfg-1.0\";\n" "+\t\treg = <0xf8007000 0x100>;\n" "+\t\tinterrupt-parent = <&intc>;\n" @@ -432,7 +449,7 @@ "+DT Overlay contains:\n" "+/dts-v1/ /plugin/;\n" "+/ {\n" - "+fragment at 0 {\n" + "+fragment@0 {\n" "+\ttarget = <&fpga_region0>;\n" "+\t#address-cells = <1>;\n" "+\t#size-cells = <1>;\n" @@ -442,7 +459,7 @@ "+\n" "+\t\tfirmware-name = \"zynq-gpio.bin\";\n" "+\n" - "+\t\tgpio1: gpio at 40000000 {\n" + "+\t\tgpio1: gpio@40000000 {\n" "+\t\t\tcompatible = \"xlnx,xps-gpio-1.00.a\";\n" "+\t\t\treg = <0x40000000 0x10000>;\n" "+\t\t\tgpio-controller;\n" @@ -463,7 +480,7 @@ "+DT Overlay contains:\n" "+/dts-v1/ /plugin/;\n" "+/ {\n" - "+\tfragment at 0 {\n" + "+\tfragment@0 {\n" "+\t\ttarget = <&fpga_region0>;\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" @@ -473,7 +490,7 @@ "+\n" "+\t\t\tfirmware-name = \"base.rbf\";\n" "+\n" - "+\t\t\tfpga-bridge at 4400 {\n" + "+\t\t\tfpga-bridge@4400 {\n" "+\t\t\t\tcompatible = \"altr,freeze-bridge\";\n" "+\t\t\t\treg = <0x4400 0x10>;\n" "+\n" @@ -485,7 +502,7 @@ "+\t\t\t\t};\n" "+\t\t\t};\n" "+\n" - "+\t\t\tfpga-bridge at 4420 {\n" + "+\t\t\tfpga-bridge@4420 {\n" "+\t\t\t\tcompatible = \"altr,freeze-bridge\";\n" "+\t\t\t\treg = <0x4420 0x10>;\n" "+\n" @@ -512,7 +529,7 @@ "+\n" "+/dts-v1/ /plugin/;\n" "+/ {\n" - "+\tfragment at 0 {\n" + "+\tfragment@0 {\n" "+\t\ttarget = <&fpga_region1>;\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" @@ -523,7 +540,7 @@ "+\t\t\tfirmware-name = \"soc_image2.rbf\";\n" "+\t\t\tpartial-fpga-config;\n" "+\n" - "+\t\t\tgpio at 10040 {\n" + "+\t\t\tgpio@10040 {\n" "+\t\t\t\tcompatible = \"altr,pio-1.0\";\n" "+\t\t\t\treg = <0x10040 0x20>;\n" "+\t\t\t\tclocks = <0x2>;\n" @@ -557,4 +574,4 @@ "-- \n" 2.10.1 -21219695d9941bbd5229859b5fcf08b3e743cc6470731b6cdf0b88350efb8588 +77894afda2aa73b3ecf264781584a0dfc40d296bcfd2c2e6c4071e17a8972175
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