From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bwLxf-0001PQ-L8 for qemu-devel@nongnu.org; Tue, 18 Oct 2016 00:25:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bwLxe-00075u-40 for qemu-devel@nongnu.org; Tue, 18 Oct 2016 00:25:11 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:60179) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bwLxc-0006x5-Hs for qemu-devel@nongnu.org; Tue, 18 Oct 2016 00:25:10 -0400 Date: Tue, 18 Oct 2016 15:04:23 +1100 From: David Gibson Message-ID: <20161018040423.GF25390@umbus.fritz.box> References: <1476719064-9242-1-git-send-email-bd.aviv@gmail.com> <1476719064-9242-4-git-send-email-bd.aviv@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Fhv9pqL4KIX+q4y7" Content-Disposition: inline In-Reply-To: <1476719064-9242-4-git-send-email-bd.aviv@gmail.com> Subject: Re: [Qemu-devel] [PATCH v4 RESEND 3/3] IOMMU: enable intel_iommu map and unmap notifiers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Aviv B.D" Cc: qemu-devel@nongnu.org, Jan Kiszka , Alex Williamson , Peter Xu , "Michael S. Tsirkin" --Fhv9pqL4KIX+q4y7 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 17, 2016 at 06:44:24PM +0300, Aviv B.D wrote: > From: "Aviv Ben-David" >=20 > Adds a list of registered vtd_as's to intel iommu state to save > iteration over each PCI device in a search of the corrosponding domain. >=20 > Signed-off-by: Aviv Ben-David > --- > hw/i386/intel_iommu.c | 102 +++++++++++++++++++++++++++++++++++= +++--- > hw/i386/intel_iommu_internal.h | 2 + > include/hw/i386/intel_iommu.h | 9 ++++ > 3 files changed, 106 insertions(+), 7 deletions(-) >=20 > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index dcf45f0..34fc1e8 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -51,6 +51,9 @@ static int vtd_dbgflags =3D VTD_DBGBIT(GENERAL) | VTD_D= BGBIT(CSR); > #define VTD_DPRINTF(what, fmt, ...) do {} while (0) > #endif > =20 > +static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num, > + uint8_t devfn, VTDContextEntry *ce); > + > static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t va= l, > uint64_t wmask, uint64_t w1cmask) > { > @@ -142,6 +145,23 @@ static uint64_t vtd_set_clear_mask_quad(IntelIOMMUSt= ate *s, hwaddr addr, > return new_val; > } > =20 > +static int vtd_get_did_dev(IntelIOMMUState *s, uint8_t bus_num, uint8_t = devfn, > + uint16_t *domain_id) > +{ > + VTDContextEntry ce; > + int ret_fr; > + > + assert(domain_id); > + > + ret_fr =3D vtd_dev_to_context_entry(s, bus_num, devfn, &ce); > + if (ret_fr) { > + return -1; > + } > + > + *domain_id =3D VTD_CONTEXT_ENTRY_DID(ce.hi); > + return 0; > +} > + > /* GHashTable functions */ > static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2) > { > @@ -683,9 +703,6 @@ static int vtd_gpa_to_slpte(VTDContextEntry *ce, uint= 64_t gpa, > *reads =3D (*reads) && (slpte & VTD_SL_R); > *writes =3D (*writes) && (slpte & VTD_SL_W); > if (!(slpte & access_right_check)) { > - VTD_DPRINTF(GENERAL, "error: lack of %s permission for " > - "gpa 0x%"PRIx64 " slpte 0x%"PRIx64, > - (flags =3D=3D IOMMU_WO ? "write" : "read"), gpa,= slpte); > return (flags =3D=3D IOMMU_RW || flags =3D=3D IOMMU_WO) ? > -VTD_FR_WRITE : -VTD_FR_READ; > } > @@ -734,9 +751,6 @@ static int vtd_dev_to_context_entry(IntelIOMMUState *= s, uint8_t bus_num, > } > =20 > if (!vtd_context_entry_present(ce)) { > - VTD_DPRINTF(GENERAL, > - "error: context-entry #%"PRIu8 "(bus #%"PRIu8 ") " > - "is not present", devfn, bus_num); > return -VTD_FR_CONTEXT_ENTRY_P; > } else if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) || > (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO)) { > @@ -1065,6 +1079,55 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMU= State *s, uint16_t domain_id) > &domain_id); > } > =20 > +static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s, > + uint16_t domain_id, hwaddr ad= dr, > + uint8_t am) > +{ > + IntelIOMMUNotifierNode *node; > + > + QLIST_FOREACH(node, &(s->notifiers_list), next) { It's not really obvious to me why you need this additional list of IntelIOMMUNotifierNode structures, rather than just the notifier list already built into each MemoryRegion. > + VTDAddressSpace *vtd_as =3D node->vtd_as; > + uint16_t vfio_domain_id; > + int ret =3D vtd_get_did_dev(s, pci_bus_num(vtd_as->bus), vtd_as-= >devfn, > + &vfio_domain_id); > + if (!ret && domain_id =3D=3D vfio_domain_id) { > + IOMMUTLBEntry entry; > + > + /* notify unmap */ > + if (node->notifier_flag & IOMMU_NOTIFIER_UNMAP) { > + VTD_DPRINTF(GENERAL, "Remove addr 0x%"PRIx64 " mask %d", > + addr, am); > + entry.target_as =3D &address_space_memory; > + entry.iova =3D addr & VTD_PAGE_MASK_4K; > + entry.translated_addr =3D 0; > + entry.addr_mask =3D ~VTD_PAGE_MASK(VTD_PAGE_SHIFT_4K + a= m); > + entry.perm =3D IOMMU_NONE; > + memory_region_notify_iommu(&node->vtd_as->iommu, entry); > + } > + > + /* notify map */ > + if (node->notifier_flag & IOMMU_NOTIFIER_MAP) { > + hwaddr original_addr =3D addr; > + VTD_DPRINTF(GENERAL, "add addr 0x%"PRIx64 " mask %d", ad= dr, am); > + while (addr < original_addr + (1 << am) * VTD_PAGE_SIZE)= { > + /* call to vtd_iommu_translate */ > + IOMMUTLBEntry entry =3D s->iommu_ops.translate( > + &node->vtd_as->= iommu, > + addr, > + IOMMU_NO_FAIL); > + if (entry.perm !=3D IOMMU_NONE) { > + addr +=3D entry.addr_mask + 1; > + memory_region_notify_iommu(&node->vtd_as->iommu,= entry); > + } else { > + addr +=3D VTD_PAGE_SIZE; > + } > + } > + } > + } > + } > +} > + > + > static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domai= n_id, > hwaddr addr, uint8_t am) > { > @@ -1075,6 +1138,8 @@ static void vtd_iotlb_page_invalidate(IntelIOMMUSta= te *s, uint16_t domain_id, > info.addr =3D addr; > info.mask =3D ~((1 << am) - 1); > g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info= ); > + > + vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am); > } > =20 > /* Flush IOTLB > @@ -2000,8 +2065,10 @@ static void vtd_iommu_notify_flag_changed(MemoryRe= gion *iommu, > IOMMUNotifierFlag new) > { > VTDAddressSpace *vtd_as =3D container_of(iommu, VTDAddressSpace, iom= mu); > + IntelIOMMUState *s =3D vtd_as->iommu_state; > + IntelIOMMUNotifierNode *node =3D NULL; > =20 > - if (new & IOMMU_NOTIFIER_MAP) { > + if (!s->cache_mode_enabled && new & IOMMU_NOTIFIER_MAP) { > error_report("Device at bus %s addr %02x.%d requires iommu " > "notifier which is currently not supported by " > "intel-iommu emulation", > @@ -2009,6 +2076,27 @@ static void vtd_iommu_notify_flag_changed(MemoryRe= gion *iommu, > PCI_FUNC(vtd_as->devfn)); > exit(1); > } > + > + /* Add new ndoe if no mapping was exising before this call */ > + if (old =3D=3D IOMMU_NOTIFIER_NONE) { > + node =3D g_malloc0(sizeof(*node)); > + node->vtd_as =3D vtd_as; > + node->notifier_flag =3D new; > + QLIST_INSERT_HEAD(&s->notifiers_list, node, next); > + return; > + } > + > + /* update notifier node with new flags */ > + QLIST_FOREACH(node, &s->notifiers_list, next) { > + if (node->vtd_as =3D=3D vtd_as) { > + if (new =3D=3D IOMMU_NOTIFIER_NONE) { > + QLIST_REMOVE(node, next); > + } else { > + node->notifier_flag =3D new; > + } > + return; > + } > + } > } > =20 > static const VMStateDescription vtd_vmstate =3D { > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_interna= l.h > index 35d9f3a..96df4ae 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -381,6 +381,8 @@ typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInf= o; > #define VTD_PAGE_SHIFT_1G 30 > #define VTD_PAGE_MASK_1G (~((1ULL << VTD_PAGE_SHIFT_1G) - 1)) > =20 > +#define VTD_PAGE_MASK(shift) (~((1ULL << (shift)) - 1)) > + > struct VTDRootEntry { > uint64_t val; > uint64_t rsvd; > diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h > index 7a94f16..c160706 100644 > --- a/include/hw/i386/intel_iommu.h > +++ b/include/hw/i386/intel_iommu.h > @@ -63,6 +63,7 @@ typedef union VTD_IR_TableEntry VTD_IR_TableEntry; > typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; > typedef struct VTDIrq VTDIrq; > typedef struct VTD_MSIMessage VTD_MSIMessage; > +typedef struct IntelIOMMUNotifierNode IntelIOMMUNotifierNode; > =20 > /* Context-Entry */ > struct VTDContextEntry { > @@ -248,6 +249,12 @@ struct VTD_MSIMessage { > /* When IR is enabled, all MSI/MSI-X data bits should be zero */ > #define VTD_IR_MSI_DATA (0) > =20 > +struct IntelIOMMUNotifierNode { > + VTDAddressSpace *vtd_as; > + IOMMUNotifierFlag notifier_flag; > + QLIST_ENTRY(IntelIOMMUNotifierNode) next; > +}; > + > /* The iommu (DMAR) device state struct */ > struct IntelIOMMUState { > X86IOMMUState x86_iommu; > @@ -285,6 +292,8 @@ struct IntelIOMMUState { > MemoryRegionIOMMUOps iommu_ops; > GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus*= reference */ > VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexe= d by bus number */ > + /* list of registered notifiers */ > + QLIST_HEAD(, IntelIOMMUNotifierNode) notifiers_list; > =20 > /* interrupt remapping */ > bool intr_enabled; /* Whether guest enabled IR */ --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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