Re: [Qemu-devel] [PATCH v2 00/15] target-sparc improvements

[no-reply@patchew.org]

Hi,

Your series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 1476844470-29763-1-git-send-email-rth@twiddle.net
Subject: [Qemu-devel] [PATCH v2 00/15] target-sparc improvements

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
27c5285 target-sparc: Use tcg_gen_atomic_cmpxchg_tl
2069f01 target-sparc: Use tcg_gen_atomic_xchg_tl
f53a73a target-sparc: Remove MMU_MODE*_SUFFIX
549a774 target-sparc: Allow 4-byte alignment on fp mem ops
d6ae826 target-sparc: Implement ldqf and stqf inline
de30bb1 target-sparc: Remove asi helper code handled inline
ea72a1b target-sparc: Implement BCOPY/BFILL inline
bc0d872 target-sparc: Implement cas_asi/casx_asi inline
1a9423b target-sparc: Implement ldstub_asi inline
b1f9907 target-sparc: Implement swap_asi inline
6d810e8 target-sparc: Handle more twinx asis
561899b target-sparc: Use MMU_PHYS_IDX for bypass asis
f6c907c target-sparc: Add MMU_PHYS_IDX
c3cc123 target-sparc: Introduce cpu_raise_exception_ra
3d4d48a target-sparc: Use overalignment flags for twinx and block asis

=== OUTPUT BEGIN ===
Checking PATCH 1/15: target-sparc: Use overalignment flags for twinx and block asis...
Checking PATCH 2/15: target-sparc: Introduce cpu_raise_exception_ra...
Checking PATCH 3/15: target-sparc: Add MMU_PHYS_IDX...
Checking PATCH 4/15: target-sparc: Use MMU_PHYS_IDX for bypass asis...
Checking PATCH 5/15: target-sparc: Handle more twinx asis...
Checking PATCH 6/15: target-sparc: Implement swap_asi inline...
Checking PATCH 7/15: target-sparc: Implement ldstub_asi inline...
Checking PATCH 8/15: target-sparc: Implement cas_asi/casx_asi inline...
Checking PATCH 9/15: target-sparc: Implement BCOPY/BFILL inline...
Checking PATCH 10/15: target-sparc: Remove asi helper code handled inline...
Checking PATCH 11/15: target-sparc: Implement ldqf and stqf inline...
Checking PATCH 12/15: target-sparc: Allow 4-byte alignment on fp mem ops...
ERROR: spaces required around that '/' (ctx:VxV)
#47: FILE: target-sparc/translate.c:2484:
+            tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
                                           ^

ERROR: spaces required around that '+' (ctx:VxV)
#47: FILE: target-sparc/translate.c:2484:
+            tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
                                             ^

total: 2 errors, 0 warnings, 175 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 13/15: target-sparc: Remove MMU_MODE*_SUFFIX...
Checking PATCH 14/15: target-sparc: Use tcg_gen_atomic_xchg_tl...
Checking PATCH 15/15: target-sparc: Use tcg_gen_atomic_cmpxchg_tl...
=== OUTPUT END ===

Test command exited with code: 1


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