From: Brian Norris <briannorris@chromium.org>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
Wenrui Li <wenrui.li@rock-chips.com>
Subject: Re: [PATCH] PCI: rockchip: fix wrong print for negotiated lane numbers
Date: Wed, 19 Oct 2016 18:39:26 -0700 [thread overview]
Message-ID: <20161020013925.GD78840@google.com> (raw)
In-Reply-To: <1476321391-6665-1-git-send-email-shawn.lin@rock-chips.com>
On Thu, Oct 13, 2016 at 09:16:31AM +0800, Shawn Lin wrote:
> The negotiated lane numbers was incorrectly calculated, fix it.
>
> Fixes: e77f847df54c6b0 ("PCI: rockchip: Add Rockchip PCIe controller support")
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> drivers/pci/host/pcie-rockchip.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index e0b22da..0d69d8c 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -549,7 +549,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
>
> /* Check the final link width from negotiated lane counter from MGMT */
> status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
> - status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
> + status = 0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
> PCIE_CORE_PL_CONF_LANE_MASK);
> dev_dbg(dev, "current link width is x%d\n", status);
>
Looks good to me:
Reviewed-by: Brian Norris <briannorris@chromium.org>
prev parent reply other threads:[~2016-10-20 1:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-13 1:16 [PATCH] PCI: rockchip: fix wrong print for negotiated lane numbers Shawn Lin
2016-10-13 1:16 ` Shawn Lin
2016-10-20 1:39 ` Brian Norris [this message]
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