From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35090) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bx7KA-0007hc-Vf for qemu-devel@nongnu.org; Thu, 20 Oct 2016 02:59:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bx7KA-0002Xl-7Y for qemu-devel@nongnu.org; Thu, 20 Oct 2016 02:59:35 -0400 From: Nicholas Piggin Date: Thu, 20 Oct 2016 17:59:10 +1100 Message-Id: <20161020065912.16132-2-npiggin@gmail.com> In-Reply-To: <20161020065912.16132-1-npiggin@gmail.com> References: <20161020065912.16132-1-npiggin@gmail.com> Subject: [Qemu-devel] [PATCH 1/3] ppc: fix MSR_ME handling for system reset interrupt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Alexey Kardashevskiy , David Gibson , Alexander Graf Power ISA specifies ME bit handling for system reset interrupt: if the interrupt occurred while the thread was in power-saving mode, set to 1; otherwise not altered Signed-off-by: Nicholas Piggin --- target-ppc/excp_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 921c39d..53c4075 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -385,11 +385,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) srr1 = SPR_BOOKE_CSRR1; break; case POWERPC_EXCP_RESET: /* System reset exception */ + /* A power-saving exception sets ME, otherwise it is unchanged */ if (msr_pow) { /* indicate that we resumed from power save mode */ msr |= 0x10000; - } else { - new_msr &= ~((target_ulong)1 << MSR_ME); + new_msr |= ((target_ulong)1 << MSR_ME); } new_msr |= (target_ulong)MSR_HVB; -- 2.9.3