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Date: Thu, 20 Oct 2016 12:23:30 +0200
From: Greg Kurz <groug@kaod.org>
Message-ID: <20161020122330.6fd279bc@bahia>
In-Reply-To: <20161020065912.16132-2-npiggin@gmail.com>
References: <20161020065912.16132-1-npiggin@gmail.com>
	<20161020065912.16132-2-npiggin@gmail.com>
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Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/3] ppc: fix MSR_ME handling
 for system reset interrupt
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To: Nicholas Piggin <npiggin@gmail.com>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, David Gibson <david@gibson.dropbear.id.au>

On Thu, 20 Oct 2016 17:59:10 +1100
Nicholas Piggin <npiggin@gmail.com> wrote:

> Power ISA specifies ME bit handling for system reset interrupt:
> 
>     if the interrupt occurred while the thread was in power-saving
>     mode, set to 1; otherwise not altered
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---

As described in "6.5 Interrupt Definitions, Figure 64" of Power ISA 3.0.

Reviewed-by: Greg Kurz <groug@kaod.org>

>  target-ppc/excp_helper.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index 921c39d..53c4075 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -385,11 +385,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
>          srr1 = SPR_BOOKE_CSRR1;
>          break;
>      case POWERPC_EXCP_RESET:     /* System reset exception                   */
> +        /* A power-saving exception sets ME, otherwise it is unchanged */
>          if (msr_pow) {
>              /* indicate that we resumed from power save mode */
>              msr |= 0x10000;
> -        } else {
> -            new_msr &= ~((target_ulong)1 << MSR_ME);
> +            new_msr |= ((target_ulong)1 << MSR_ME);
>          }
>  
>          new_msr |= (target_ulong)MSR_HVB;