From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org#v4.6+
Subject: Re: [PATCH 1/2] drm/i915/fbc: fix CFB size calculation for gen8+
Date: Fri, 21 Oct 2016 19:07:07 +0300 [thread overview]
Message-ID: <20161021160707.GV4329@intel.com> (raw)
In-Reply-To: <1477065346-13736-1-git-send-email-paulo.r.zanoni@intel.com>
On Fri, Oct 21, 2016 at 01:55:45PM -0200, Paulo Zanoni wrote:
> Broadwell and newer actually compress up to 2560 lines instead of 2048
> (as documented in the FBC_CTL page). If we don't take this into
> consideration we end up reserving too little stolen memory for the
> CFB, so we may allocate something else (such as a ring) right after
> what we reserved, and the hardware will overwrite it with the contents
> of the CFB when FBC is active, causing GPU hangs. Another possibility
> is that the CFB may be allocated at the very end of the available
> space, so the CFB will overlap the reserved stolen area, leading to
> FIFO underruns.
>
> This bug has always been a problem on BDW (the only affected platform
> where FBC is enabled by default), but it's much easier to reproduce
> since the following commit:
> commit c58b735fc762e891481e92af7124b85cb0a51fce
> Author: Chris Wilson <chris@chris-wilson.co.uk>
> Date: Thu Aug 18 17:16:57 2016 +0100
> drm/i915: Allocate rings from stolen
>
> Of course, you can only reproduce the bug if your screen is taller
> than 2048 lines.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98213
> Fixes: a98ee79317b4 ("drm/i915/fbc: enable FBC by default on HSW and BDW")
> Cc: <stable@vger.kernel.org> # v4.6+
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_fbc.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 617189a..6345cb8 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -104,8 +104,10 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
> int lines;
>
> intel_fbc_get_plane_source_size(cache, NULL, &lines);
> - if (INTEL_INFO(dev_priv)->gen >= 7)
> + if (INTEL_GEN(dev_priv) == 7)
> lines = min(lines, 2048);
> + else if (INTEL_GEN(dev_priv) >= 8)
> + lines = min(lines, 2560);
>
> /* Hardware needs the full buffer stride, not just the active area. */
> return lines * cache->fb.stride;
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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next prev parent reply other threads:[~2016-10-21 16:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-21 15:55 [PATCH 1/2] drm/i915/fbc: fix CFB size calculation for gen8+ Paulo Zanoni
2016-10-21 15:55 ` [PATCH 2/2] drm/i915/fbc: fix FBC_COMPRESSION_MASK on BDW+ Paulo Zanoni
2016-10-21 16:08 ` Ville Syrjälä
2016-10-21 16:07 ` Ville Syrjälä [this message]
2016-10-21 17:16 ` ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/fbc: fix CFB size calculation for gen8+ Patchwork
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