From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1byVww-0000R2-43 for qemu-devel@nongnu.org; Sun, 23 Oct 2016 23:29:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1byVwt-0005el-1g for qemu-devel@nongnu.org; Sun, 23 Oct 2016 23:29:22 -0400 Date: Mon, 24 Oct 2016 12:16:19 +1100 From: David Gibson Message-ID: <20161024011619.GE19629@umbus.fritz.box> References: <20161020065912.16132-1-npiggin@gmail.com> <20161020065912.16132-3-npiggin@gmail.com> <20161021004058.074a7769@roar.ozlabs.ibm.com> <20161021010954.GY11140@umbus.fritz.box> <20161021153543.294dfa9d@roar.ozlabs.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="6Vw0j8UKbyX0bfpA" Content-Disposition: inline In-Reply-To: <20161021153543.294dfa9d@roar.ozlabs.ibm.com> Subject: Re: [Qemu-devel] [PATCH v2] ppc: allow certain HV interrupts to be delivered to guests List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nicholas Piggin Cc: =?iso-8859-1?Q?C=E9dric?= Le Goater , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Benjamin Herrenschmidt --6Vw0j8UKbyX0bfpA Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Oct 21, 2016 at 03:35:43PM +1100, Nicholas Piggin wrote: > On Fri, 21 Oct 2016 12:09:54 +1100 > David Gibson wrote: >=20 > > On Fri, Oct 21, 2016 at 12:40:58AM +1100, Nicholas Piggin wrote: > > > On Thu, 20 Oct 2016 15:08:07 +0200 > > > C=E9dric Le Goater wrote: > > > =20 > > > > On 10/20/2016 08:59 AM, Nicholas Piggin wrote: =20 > > > > > Signed-off-by: Nicholas Piggin > > > > > --- > > > > > target-ppc/excp_helper.c | 8 ++++++-- > > > > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > >=20 > > > > > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c > > > > > index 53c4075..477af10 100644 > > > > > --- a/target-ppc/excp_helper.c > > > > > +++ b/target-ppc/excp_helper.c > > > > > @@ -390,9 +390,13 @@ static inline void powerpc_excp(PowerPCCPU *= cpu, int excp_model, int excp) > > > > > /* indicate that we resumed from power save mode */ > > > > > msr |=3D 0x10000; > > > > > new_msr |=3D ((target_ulong)1 << MSR_ME); > > > > > + new_msr |=3D (target_ulong)MSR_HVB; > > > > > + } else { > > > > > + /* The ISA specifies the HV bit is set when the hardware in= terrupt > > > > > + * is raised, however when hypervisors deliver the exceptio= n to > > > > > + * guests, it should not be set. > > > > > + */ > > > > > } > > > > > - > > > > > - new_msr |=3D (target_ulong)MSR_HVB; > > > > > ail =3D 0; > > > > > break; > > > > > case POWERPC_EXCP_DSEG: /* Data segment exception = */ > > > > > =20 > > > >=20 > > > > should not that be cleared later on in powerpc_excp() by : > > > >=20 > > > > env->msr =3D new_msr & env->msr_mask; > > > >=20 > > > > ? but the routine is rather long so I might be missing a branch. = =20 > > >=20 > > > No you're right, so it can't leak into the guest, phew! > > >=20 > > > The problem I get is the interrupt code doing some things differently > > > depending on on the HV bit. For example what I noticed is the guest > > > losing its LE bit upon entry. > > >=20 > > > Perhaps a cleaner way is for the system reset case to set new_msr > > > according to the ISA, and then apply the msr_mask (or at least mask > > > out HV) before calculating the exception model? Any preference? =20 > >=20 > > I think the proposed revision makes sense. > >=20 >=20 > What do you think of this version? This fixes up machine check guest > delivery as well. I'm sending this ahead of the new hcall patch, because > it's a bugfix for existing code. I'll get around to the hcall again next > week. >=20 > Thanks, > Nick >=20 >=20 > ppc hypervisors have delivered system reset and machine check exception > interrupts to guests in some situations (e.g., see FWNMI feature of LoPAP= R, > or NMI injection in QEMU). >=20 > These exceptions are architected to set the HV bit in hardware, however > when injected into a guest, the HV bit should be cleared. Current code > masks off the HV bit before setting the new MSR, however this happens aft= er > the interrupt delivery model has calculated delivery mode for the excepti= on. > This can result in the guest's MSR LE bit being lost. >=20 > Provide a new flag for HV exceptions to allow delivery to guests. The > exception model masks out the HV bit. >=20 > Also add another sanity check to ensure other such exceptions don't try > to set HV in guest without setting guest_hv_excp >=20 > Signed-off-by: Nicholas Piggin > --- > target-ppc/excp_helper.c | 25 ++++++++++++++++++++++--- > 1 file changed, 22 insertions(+), 3 deletions(-) >=20 > diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c > index 53c4075..1b18433 100644 > --- a/target-ppc/excp_helper.c > +++ b/target-ppc/excp_helper.c > @@ -77,7 +77,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) > CPUState *cs =3D CPU(cpu); > CPUPPCState *env =3D &cpu->env; > target_ulong msr, new_msr, vector; > - int srr0, srr1, asrr0, asrr1, lev, ail; > + int srr0, srr1, asrr0, asrr1, lev, ail, guest_hv_excp; So, to clarify my understanding of this. The guest_hv_excp flag indicates that this is a normally-HV exception which *could* be delivered to a guest with HV clear, *not* that we're actually doing so in this instance. Yes? > bool lpes0; > =20 > qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx > @@ -149,6 +149,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int= excp_model, int excp) > * > * AIL is initialized here but can be cleared by > * selected exceptions > + * > + * guest_hv_excp is a provision to raise HV architected > + * exceptions in guests by delivering them with HV bit > + * clear. System reset and machine check use this. > */ > #if defined(TARGET_PPC64) > if (excp_model =3D=3D POWERPC_EXCP_POWER7 || > @@ -165,6 +169,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) > lpes0 =3D true; > ail =3D 0; > } > + guest_hv_excp =3D 0; > =20 > /* Hypervisor emulation assistance interrupt only exists on server > * arch 2.05 server or later. We also don't want to generate it if > @@ -214,6 +219,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) > cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; > } > new_msr |=3D (target_ulong)MSR_HVB; > + guest_hv_excp =3D 1; > ail =3D 0; > =20 > /* machine check exceptions don't have ME set */ > @@ -391,8 +397,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int = excp_model, int excp) > msr |=3D 0x10000; > new_msr |=3D ((target_ulong)1 << MSR_ME); > } > - > new_msr |=3D (target_ulong)MSR_HVB; > + guest_hv_excp =3D 1; > ail =3D 0; > break; > case POWERPC_EXCP_DSEG: /* Data segment exception = */ > @@ -610,10 +616,23 @@ static inline void powerpc_excp(PowerPCCPU *cpu, in= t excp_model, int excp) > =20 > /* Sanity check */ > if (!(env->msr_mask & MSR_HVB) && (srr0 =3D=3D SPR_HSRR0)) { > - cpu_abort(cs, "Trying to deliver HV exception %d with " > + cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " > "no HV support\n", excp); > } > =20 > + /* The ISA specifies the HV bit is set when the hardware interrupt > + * is raised, however in some cases hypervisors deliver the exception > + * to guests. HV should be cleared in that case. > + */ > + if (!(env->msr_mask & MSR_HVB) && (new_msr & MSR_HVB)) { > + if (guest_hv_excp) { > + new_msr &=3D ~MSR_HVB; > + } else { > + cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " > + "no HV support\n", excp); > + } > + } > + > /* If any alternate SRR register are defined, duplicate saved values= */ > if (asrr0 !=3D -1) { > env->spr[asrr0] =3D env->spr[srr0]; --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --6Vw0j8UKbyX0bfpA Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYDWDjAAoJEGw4ysog2bOSeHYQAOXsEzdzE7qgn8l9hqxG4ud8 HOil4xFtwr+mXvIXSxeYTf4R5nWZNSPGU8qAWf685hLgtBxKVbPDWM2h9QJOvbjb VYGFgaVdRSwJ6k3NwtvzGYyqyjo+ToHQedsPj9+7pHUjAfUcyJV6JCER+Mh6uGcT 7jWMtfN18qZ14vxUwSUl+xlg91OqVqXwMnQuoJNYaLUYI8MFAuKTZviP5Eam0X2W HB6e7HN4SeBdLGmZ1u+sITtMH2IJ6VJYOv3G6rnevFpgaN7FM6L9xsVfgA9tebhq e9j5TQzsV0RKHFdIScx74INlssEM0Omezs3PUwbakMM3dYi5kwmHN83tSuMg0gwA YPeiOHuWoqO1H2W+kU4CijNkL0/46gkcGg0BHmJGZ7pvebPtJ9iM57ddgokyEgHT +oV0TX12xAzwBjEuH2lrMu5K1gB6cCeW/cgmq3qpNoT6c7p7Ukjudyd91+7NndkM aXFrwW/+vdqQsMwsPojJ0L5gNsKt1d10wKuLHpiWOCxifDTRrBRkZ2NSMTOTspH4 6bT54r67oQpr8FNPQaQo+bCsdC7/B41/YDzy93wjDvaY03FuUMy1z26z8wmqgt3t NW5BI+jH3RL1G0mHaWQQws4zNy125wPeHv7Dnd32YRbJmP8JOZfGvhvzsmHlg3C5 SxPhL9BS/eikyBhsaneM =gVXu -----END PGP SIGNATURE----- --6Vw0j8UKbyX0bfpA--