From: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
To: Mark Brown <broonie@kernel.org>
Cc: brian.austin@cirrus.com, alsa-devel@alsa-project.org,
lgirdwood@gmail.com, Paul.Handrigan@cirrus.com,
patches@opensource.wolfsonmicro.com
Subject: Re: [PATCH 1/6] ASoC: cs42xx8: Mark chip ID as volatile and remove cache bypass
Date: Tue, 25 Oct 2016 16:16:05 +0100 [thread overview]
Message-ID: <20161025151605.GC28180@localhost.localdomain> (raw)
In-Reply-To: <20161024153342.GA17252@sirena.org.uk>
On Mon, Oct 24, 2016 at 04:33:42PM +0100, Mark Brown wrote:
> On Mon, Oct 24, 2016 at 10:55:44AM +0100, Charles Keepax wrote:
> > Rather than manually enabling cache bypass when reading the ID registers
> > simply mark them as volatile. The old code worked this is simply the
> > more standard way to implement this. There is a comment included in the
>
> Even better just remove the register default, with rbtree regmap will do
> the read and then cache it - no need to mark as volatile.
:-) well if we are preferring that then some of the series can
just be dropped, as they were changing exactly that to be
explicitly marked volatile.
I will fixup the remaining patches and resend.
Thanks,
Charles
prev parent reply other threads:[~2016-10-25 15:15 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-24 9:55 [PATCH 1/6] ASoC: cs42xx8: Mark chip ID as volatile and remove cache bypass Charles Keepax
2016-10-24 9:55 ` [PATCH 2/6] ASoC: cs42l73: Make ID registers " Charles Keepax
2016-10-24 9:55 ` [PATCH 3/6] ASoC: cs42l56: " Charles Keepax
2016-10-24 9:55 ` [PATCH 4/6] ASoC: cs4265: Mark chip ID register as volatile Charles Keepax
2016-10-24 9:55 ` [PATCH 5/6] ASoC: cs42l52: " Charles Keepax
2016-10-24 9:55 ` [PATCH 6/6] ASoC: cs53l30: Mark chip ID registers " Charles Keepax
2016-10-24 12:55 ` [PATCH 1/6] ASoC: cs42xx8: Mark chip ID as volatile and remove cache bypass Brian Austin
2016-10-24 15:33 ` Mark Brown
2016-10-25 15:16 ` Charles Keepax [this message]
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