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From: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: [PATCH v2 05/14] secboot: remove fixup_hs_desc hook
Date: Thu, 27 Oct 2016 13:36:59 +0900	[thread overview]
Message-ID: <20161027043708.22538-6-acourbot@nvidia.com> (raw)
In-Reply-To: <20161027043708.22538-1-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

This hook can be removed if the function writing the HS
descriptor is aware of WPR settings. Let's do that as it allows us to
make the ACR descriptor structure private and save some code.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
 drm/nouveau/nvkm/subdev/secboot/gm200.c | 95 ++++++++++++++++++++++++---------
 drm/nouveau/nvkm/subdev/secboot/gm20b.c | 11 ----
 drm/nouveau/nvkm/subdev/secboot/priv.h  | 60 +++------------------
 3 files changed, 79 insertions(+), 87 deletions(-)

diff --git a/drm/nouveau/nvkm/subdev/secboot/gm200.c b/drm/nouveau/nvkm/subdev/secboot/gm200.c
index b020e41d2391..e1c51f8293c8 100644
--- a/drm/nouveau/nvkm/subdev/secboot/gm200.c
+++ b/drm/nouveau/nvkm/subdev/secboot/gm200.c
@@ -771,7 +771,7 @@ ls_ucode_mgr_write_wpr(struct gm200_secboot *gsb, struct ls_ucode_mgr *mgr,
 			u8 desc[gsb->func->bl_desc_size];
 			struct gm200_flcn_bl_desc gdesc;
 
-			ls_ucode_img_populate_bl_desc(img, gsb->wpr_addr,
+			ls_ucode_img_populate_bl_desc(img, gsb->acr_wpr_addr,
 						      &gdesc);
 			gsb->func->fixup_bl_desc(&gdesc, &desc);
 			nvkm_gpuobj_memcpy_to(wpr_blob,
@@ -846,8 +846,11 @@ gm200_secboot_prepare_ls_blob(struct gm200_secboot *gsb)
 
 	/* If WPR address and size are not fixed, set them to fit the LS blob */
 	if (!gsb->wpr_size) {
-		gsb->wpr_addr = gsb->ls_blob->addr;
-		gsb->wpr_size = gsb->ls_blob->size;
+		gsb->acr_wpr_addr = gsb->ls_blob->addr;
+		gsb->acr_wpr_size = gsb->ls_blob->size;
+	} else {
+		gsb->acr_wpr_addr = gsb->wpr_addr;
+		gsb->acr_wpr_size = gsb->wpr_size;
 	}
 
 	/* Write LS blob */
@@ -925,6 +928,69 @@ gm200_secboot_populate_hsf_bl_desc(void *acr_image,
 }
 
 /**
+ * struct hsflcn_acr_desc - data section of the HS firmware
+ *
+ * This header is to be copied at the beginning of DMEM by the HS bootloader.
+ *
+ * @signature:		signature of ACR ucode
+ * @wpr_region_id:	region ID holding the WPR header and its details
+ * @wpr_offset:		offset from the WPR region holding the wpr header
+ * @regions:		region descriptors
+ * @nonwpr_ucode_blob_size:	size of LS blob
+ * @nonwpr_ucode_blob_start:	FB location of LS blob is
+ */
+struct hsflcn_acr_desc {
+	union {
+		u8 reserved_dmem[0x200];
+		u32 signatures[4];
+	} ucode_reserved_space;
+	u32 wpr_region_id;
+	u32 wpr_offset;
+	u32 mmu_mem_range;
+#define FLCN_ACR_MAX_REGIONS 2
+	struct {
+		u32 no_regions;
+		struct {
+			u32 start_addr;
+			u32 end_addr;
+			u32 region_id;
+			u32 read_mask;
+			u32 write_mask;
+			u32 client_mask;
+		} region_props[FLCN_ACR_MAX_REGIONS];
+	} regions;
+	u32 ucode_blob_size;
+	u64 ucode_blob_base __aligned(8);
+	struct {
+		u32 vpr_enabled;
+		u32 vpr_start;
+		u32 vpr_end;
+		u32 hdcp_policies;
+	} vpr_desc;
+};
+
+static void
+gm200_secboot_fixup_hs_desc(struct gm200_secboot *gsb,
+			    struct hsflcn_acr_desc *desc)
+{
+	desc->ucode_blob_base = gsb->ls_blob->addr;
+	desc->ucode_blob_size = gsb->ls_blob->size;
+
+	desc->wpr_offset = 0;
+
+	/* WPR region information if WPR is not fixed */
+	if (gsb->wpr_size == 0) {
+		desc->wpr_region_id = 1;
+		desc->regions.no_regions = 1;
+		desc->regions.region_props[0].region_id = 1;
+		desc->regions.region_props[0].start_addr =
+							 gsb->acr_wpr_addr >> 8;
+		desc->regions.region_props[0].end_addr =
+				   (gsb->acr_wpr_addr + gsb->acr_wpr_size) >> 8;
+	}
+}
+
+/**
  * gm200_secboot_prepare_hs_blob - load and prepare a HS blob and BL descriptor
  *
  * @gsb secure boot instance to prepare for
@@ -957,12 +1023,12 @@ gm200_secboot_prepare_hs_blob(struct gm200_secboot *gsb, const char *fw,
 
 	acr_data = acr_image + hsbin_hdr->data_offset;
 
-	/* Patch descriptor? */
+	/* Patch descriptor with WPR information? */
 	if (patch) {
 		fw_hdr = acr_image + hsbin_hdr->header_offset;
 		load_hdr = acr_image + fw_hdr->hdr_offset;
 		desc = acr_data + load_hdr->data_dma_base;
-		gsb->func->fixup_hs_desc(gsb, desc);
+		gm200_secboot_fixup_hs_desc(gsb, desc);
 	}
 
 	/* Generate HS BL descriptor */
@@ -1404,29 +1470,10 @@ gm200_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc *desc, void *ret)
 	memcpy(ret, desc, sizeof(*desc));
 }
 
-static void
-gm200_secboot_fixup_hs_desc(struct gm200_secboot *gsb,
-			    struct hsflcn_acr_desc *desc)
-{
-	desc->ucode_blob_base = gsb->ls_blob->addr;
-	desc->ucode_blob_size = gsb->ls_blob->size;
-
-	desc->wpr_offset = 0;
-
-	/* WPR region information for the HS binary to set up */
-	desc->wpr_region_id = 1;
-	desc->regions.no_regions = 1;
-	desc->regions.region_props[0].region_id = 1;
-	desc->regions.region_props[0].start_addr = gsb->wpr_addr >> 8;
-	desc->regions.region_props[0].end_addr =
-		(gsb->wpr_addr + gsb->wpr_size) >> 8;
-}
-
 static const struct gm200_secboot_func
 gm200_secboot_func = {
 	.bl_desc_size = sizeof(struct gm200_flcn_bl_desc),
 	.fixup_bl_desc = gm200_secboot_fixup_bl_desc,
-	.fixup_hs_desc = gm200_secboot_fixup_hs_desc,
 	.prepare_blobs = gm200_secboot_prepare_blobs,
 };
 
diff --git a/drm/nouveau/nvkm/subdev/secboot/gm20b.c b/drm/nouveau/nvkm/subdev/secboot/gm20b.c
index 1cb663c31e17..3d9f3748864f 100644
--- a/drm/nouveau/nvkm/subdev/secboot/gm20b.c
+++ b/drm/nouveau/nvkm/subdev/secboot/gm20b.c
@@ -99,21 +99,10 @@ gm20b_secboot_fixup_bl_desc(const struct gm200_flcn_bl_desc *desc, void *ret)
 	gdesc->data_size = desc->data_size;
 }
 
-static void
-gm20b_secboot_fixup_hs_desc(struct gm200_secboot *gsb,
-			    struct hsflcn_acr_desc *desc)
-{
-	desc->ucode_blob_base = gsb->ls_blob->addr;
-	desc->ucode_blob_size = gsb->ls_blob->size;
-
-	desc->wpr_offset = 0;
-}
-
 static const struct gm200_secboot_func
 gm20b_secboot_func = {
 	.bl_desc_size = sizeof(struct gm20b_flcn_bl_desc),
 	.fixup_bl_desc = gm20b_secboot_fixup_bl_desc,
-	.fixup_hs_desc = gm20b_secboot_fixup_hs_desc,
 	.prepare_blobs = gm20b_secboot_prepare_blobs,
 };
 
diff --git a/drm/nouveau/nvkm/subdev/secboot/priv.h b/drm/nouveau/nvkm/subdev/secboot/priv.h
index baa802b1e9d2..ce0f3c87212b 100644
--- a/drm/nouveau/nvkm/subdev/secboot/priv.h
+++ b/drm/nouveau/nvkm/subdev/secboot/priv.h
@@ -91,48 +91,6 @@ struct gm200_flcn_bl_desc {
 };
 
 /**
- * struct hsflcn_acr_desc - data section of the HS firmware
- *
- * This header is to be copied at the beginning of DMEM by the HS bootloader.
- *
- * @signature:		signature of ACR ucode
- * @wpr_region_id:	region ID holding the WPR header and its details
- * @wpr_offset:		offset from the WPR region holding the wpr header
- * @regions:		region descriptors
- * @nonwpr_ucode_blob_size:	size of LS blob
- * @nonwpr_ucode_blob_start:	FB location of LS blob is
- */
-struct hsflcn_acr_desc {
-	union {
-		u8 reserved_dmem[0x200];
-		u32 signatures[4];
-	} ucode_reserved_space;
-	u32 wpr_region_id;
-	u32 wpr_offset;
-	u32 mmu_mem_range;
-#define FLCN_ACR_MAX_REGIONS 2
-	struct {
-		u32 no_regions;
-		struct {
-			u32 start_addr;
-			u32 end_addr;
-			u32 region_id;
-			u32 read_mask;
-			u32 write_mask;
-			u32 client_mask;
-		} region_props[FLCN_ACR_MAX_REGIONS];
-	} regions;
-	u32 ucode_blob_size;
-	u64 ucode_blob_base __aligned(8);
-	struct {
-		u32 vpr_enabled;
-		u32 vpr_start;
-		u32 vpr_end;
-		u32 hdcp_policies;
-	} vpr_desc;
-};
-
-/**
  * Contains the whole secure boot state, allowing it to be performed as needed
  * @wpr_addr:		physical address of the WPR region
  * @wpr_size:		size in bytes of the WPR region
@@ -154,14 +112,19 @@ struct gm200_secboot {
 	const struct gm200_secboot_func *func;
 
 	/*
-	 * Address and size of the WPR region. On dGPU this will be the
-	 * address of the LS blob. On Tegra this is a fixed region set by the
-	 * bootloader
+	 * Address and size of the fixed WPR region, if any. On Tegra this
+	 * region is set by the bootloader
 	 */
 	u64 wpr_addr;
 	u32 wpr_size;
 
 	/*
+	 * Address and size of the actual WPR region.
+	 */
+	u64 acr_wpr_addr;
+	u32 acr_wpr_size;
+
+	/*
 	 * HS FW - lock WPR region (dGPU only) and load LS FWs
 	 * on Tegra the HS FW copies the LS blob into the fixed WPR instead
 	 */
@@ -203,7 +166,6 @@ struct gm200_secboot {
  * @fixup_bl_desc:	hook that generates the proper BL descriptor format from
  *			the generic GM200 format into a data array of size
  *			bl_desc_size
- * @fixup_hs_desc:	hook that twiddles the HS descriptor before it is used
  * @prepare_blobs:	prepares the various blobs needed for secure booting
  */
 struct gm200_secboot_func {
@@ -215,12 +177,6 @@ struct gm200_secboot_func {
 	u32 bl_desc_size;
 	void (*fixup_bl_desc)(const struct gm200_flcn_bl_desc *, void *);
 
-	/*
-	 * Chip-specific modifications of the HS descriptor can be done here.
-	 * On dGPU this is used to fill the information about the WPR region
-	 * we want the HS FW to set up.
-	 */
-	void (*fixup_hs_desc)(struct gm200_secboot *, struct hsflcn_acr_desc *);
 	int (*prepare_blobs)(struct gm200_secboot *);
 };
 
-- 
2.10.0

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  parent reply	other threads:[~2016-10-27  4:36 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-27  4:36 [PATCH v2 00/14] Secure Boot refactoring Alexandre Courbot
     [not found] ` <20161027043708.22538-1-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-10-27  4:36   ` [PATCH v2 01/14] core: constify nv*_printk macros Alexandre Courbot
2016-10-27  4:36   ` [PATCH v2 02/14] core: add falcon library Alexandre Courbot
2016-10-27  4:36   ` [PATCH v2 03/14] secboot: use falcon library's IMEM/DMEM loading functions Alexandre Courbot
2016-10-27  4:36   ` [PATCH v2 04/14] secboot: rename init() hook to oneinit() Alexandre Courbot
2016-10-27  4:36   ` Alexandre Courbot [this message]
2016-10-27  4:37   ` [PATCH v2 06/14] secboot: add low-secure firmware hooks Alexandre Courbot
2016-10-27  4:37   ` [PATCH v2 07/14] secboot: generate HS BL descriptor in hook Alexandre Courbot
2016-10-27  4:37   ` [PATCH v2 08/14] secboot: reorganize into more files Alexandre Courbot
2016-10-27  4:37   ` [PATCH v2 09/14] secboot: add LS flags to LS func structure Alexandre Courbot
2016-10-27  4:37   ` [PATCH v2 10/14] secboot: split reset function Alexandre Courbot
2016-10-27  4:37   ` [PATCH v2 11/14] secboot: disable falcon interrupts before running Alexandre Courbot
2016-10-27  4:37   ` [PATCH v2 12/14] secboot: remove unneeded ls_ucode_img member Alexandre Courbot
2016-10-27  4:37   ` [PATCH v2 13/14] secboot: remove ls_ucode_mgr Alexandre Courbot
2016-10-27  4:37   ` [PATCH v2 14/14] secboot: abstract LS firmware loading functions Alexandre Courbot
2016-10-27  8:27   ` [PATCH v2 00/14] Secure Boot refactoring Alexandre Courbot

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