From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c1HJt-0008H7-4o for qemu-devel@nongnu.org; Mon, 31 Oct 2016 14:28:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c1HJo-0002Gb-Vl for qemu-devel@nongnu.org; Mon, 31 Oct 2016 14:28:29 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:58854 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c1HJo-0002GW-P9 for qemu-devel@nongnu.org; Mon, 31 Oct 2016 14:28:24 -0400 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u9VINfPJ131798 for ; Mon, 31 Oct 2016 14:28:24 -0400 Received: from e24smtp02.br.ibm.com (e24smtp02.br.ibm.com [32.104.18.86]) by mx0b-001b2d01.pphosted.com with ESMTP id 26e5hq65vx-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 31 Oct 2016 14:28:24 -0400 Received: from localhost by e24smtp02.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 31 Oct 2016 16:28:22 -0200 Received: from d24relay01.br.ibm.com (d24relay01.br.ibm.com [9.8.31.16]) by d24dlp01.br.ibm.com (Postfix) with ESMTP id 5AE17352005C for ; Mon, 31 Oct 2016 14:27:51 -0400 (EDT) Received: from d24av05.br.ibm.com (d24av05.br.ibm.com [9.18.232.44]) by d24relay01.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u9VISI4d4923396 for ; Mon, 31 Oct 2016 16:28:18 -0200 Received: from d24av05.br.ibm.com (localhost [127.0.0.1]) by d24av05.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u9VISIYA016412 for ; Mon, 31 Oct 2016 16:28:18 -0200 Date: Mon, 31 Oct 2016 16:28:14 -0200 From: joserz@linux.vnet.ibm.com References: <1477676782-21378-1-git-send-email-joserz@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Message-Id: <20161031182814.GB15738@pacoca> Subject: Re: [Qemu-devel] [PATCH Risu 0/3] Risu support for PPC64LE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers On Mon, Oct 31, 2016 at 02:45:24PM +0000, Peter Maydell wrote: > On 28 October 2016 at 18:46, Jose Ricardo Ziviani > wrote: > > From: Jose Ricardo Ziviani > > > > This is an initial effort to have RISU working for PPC64LE. > > > > I also made some changes to isolate risugen, creating two modules > > (risugen_arm.pm and risugen_ppc64le.pm) to implement specific > > instructions in it. > > > > Suggestions are welcome! :) > > > > TODOS: > > - improve load/store instruction generation > > - improve initial random values for FP and Vector regs. > > > > Jose Ricardo Ziviani (3): > > Implementation of ppc64le module for risugen and risufile > > Isolates Arm specific subroutines out from risugen main file > > Initial implemention for ppc64le > > Thanks for this patchset. The modularisation of architecture > support in particular is something we've needed for a while. > > I've made a few first-pass review comments and some suggestions > for breaking up the patchset to make it a bit easier to review. > I'll try to go easy on the review requirements since this is > fundamentally just a test tool. > > Getting the copyright statements right is really important > though -- I can't apply it without those being fixed. > > thanks > -- PMM > I thank you for reviewing it, really appreciate that. I'll break it up in smaller pieces, apply the suggestions, and send a v2 soon. Thank you! Ziviani