[PATCH] clk: rockchip: add 400MHz to rk3066 clock rates table

From: "Paweł Jarosz" <paweljarosz3691-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org,
	sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
	heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	paweljarosz3691-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Subject: [PATCH] clk: rockchip: add 400MHz to rk3066 clock rates table
Date: Fri, 4 Nov 2016 14:10:56 +0100	[thread overview]
Message-ID: <20161104131056.GA9801@vaio-ubuntu> (raw)

We need this to init PLL_CPLL to 400MHz at boot.

Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com>
---
 drivers/clk/rockchip/clk-rk3188.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index a6d398f..062ef49 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
 	RK3066_PLL_RATE( 504000000, 1, 84, 4),
 	RK3066_PLL_RATE( 456000000, 1, 76, 4),
 	RK3066_PLL_RATE( 408000000, 1, 68, 4),
+	RK3066_PLL_RATE( 400000000, 3, 100, 2),
 	RK3066_PLL_RATE( 384000000, 2, 128, 4),
 	RK3066_PLL_RATE( 360000000, 1, 60, 4),
 	RK3066_PLL_RATE( 312000000, 1, 52, 4),
-- 
2.7.4


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